Document Outline

• Contents
• Introduction
  • 1.1 Kibra 380 or Kibra 480 Overview
    • 1.1.1 Receiving Your Kibra 380 or Kibra 480
    • 1.1.2 Unpacking the Kibra 380 or Kibra 480
    • 1.1.3 Kibra 380 or Kibra 480 Features
    • 1.1.4 Difference between Kibra 380 or Kibra 480
      • CMD/ADD/CNTRL Bus and Process JEDEC Protocol
      • Clock-Based Timing
      • DIMM Slot Protocol
    • 1.1.5 Trigger
    • 1.1.6 Kibra 380 or Kibra 480 Front Panel
  • 1.2 Specifications
    • 1.2.1 Package
    • 1.2.2 Power Requirements
    • 1.2.3 Environmental Conditions
    • 1.2.4 Switches
    • 1.2.5 LEDs
    • 1.2.6 Recording Memory Size
  • 1.3 Installing Your Kibra 380 or Kibra 480 Protocol Analyzer
    • Software Installation
    • System Restart
    • Error Message
  • 1.4 Hardware Setup
    • 1.4.1 Connecting in General
      • Power on Procedure
  • 1.5 DDR Interposer
    • 1.5.1 Kibra 380 or Kibra 480 Slot 1 Interposer
    • 1.5.2 Kibra 380 or Kibra 480 Slot 2 Interposer
    • 1.5.3 External Trigger Out
    • 1.5.4 External Trigger In
    • 1.5.5 Low Latency Read/Write Trigger Out
    • 1.5.6 Daisy Chaining
      • Daisy Chaining
  • 1.6 CrossSync Control Panel
  • 1.7 Launching Your Kibra 380 or Kibra 480 Software
    • 1.7.1 Establish Interface
    • 1.7.2 About
  • 1.8 Using the Software
  • 1.9 Protocol Analyzer
    • 1.9.1 Viewing Captured Data
    • 1.9.2 JEDEC Triggers
• Protocol Analysis
  • 2.1 Main Window
  • 2.2 Software Menus and Toolbar
  • 2.3 Application Menu Options
  • 2.4 File
  • 2.5 Setup
  • 2.6 Recording Options Setup
    • 2.6.1 Recording Options - General Tab
      • Product
      • Recording Type: Trigger Mode
      • Snapshot Mode
      • Manual Trigger Mode
      • Event Trigger Mode
      • Buffer Size
      • Trigger Position
      • Note
      • Trace Filename & Path
      • Capture
    • 2.6.2 Recording Options - Basic Settings Tab
      • DRAM Type
      • LRDIMM Support
      • Mirrored
      • ECC
      • Encoded
      • Follow MRS Settings
      • Memory Controller
      • Active Ranks
      • Active Banks
      • Command Filter Out
      • Timing Violation Trigger
      • Handling Timing Violation in MPR states (DDR4)
      • Protocol Violation Trigger
      • Alert Trigger (DDR4)
    • 2.6.3 Recording Options - Advanced Triggers Tab
      • Command Trigger
      • RCW/BCW Commands Trigger
      • Read/Write Trigger
      • Sequence Trigger
      • Clock Present
    • 2.6.4 Recording Options - Memory Address Mapping Tab
      • Read/Write on Specific Address Trigger
      • Decoding Read/Write Commands in Waveform/Listing View
      • Search on System Address
  • 2.7 Devices
  • 2.8 CrossSync Control Panel
    • 2.8.1 Launching the CrossSync Control Panel
  • 2.9 Preferences
    • 2.9.1 General
    • 2.9.2 DDR3 Lines Properties
    • 2.9.3 DDR4 Lines Properties
    • 2.9.4 Symbol Coloring
    • 2.9.5 Waveform View
    • 2.9.6 Listing View
    • 2.9.7 Bank State View
    • 2.9.8 RTS View
  • 2.10 Reset Interposers
  • 2.11 Init Phy
  • 2.12 Session
  • 2.13 Analysis
  • 2.14 Waveform View
  • 2.15 Listing View
  • 2.16 Bank State View
  • 2.17 Traffic Summary
  • 2.18 Timing Calculator View
  • 2.19 Last MRS Values
  • 2.20 Row Usage Report
  • 2.21 Timing Violation Analysis
  • 2.22 Trace Info
    • 2.22.1 Recording Options Summary
  • 2.23 Navigation
  • 2.24 View
  • 2.25 Window
  • 2.26 Help
    • Tell Teledyne LeCroy
    • User Manual (F1)
    • Video Tutorials
    • Display License Information
    • Update License
    • Register Product Online
    • Check for Updates
    • Shortcut List
    • About
  • 2.27 Example Files
    • Run a Sample Analysis
    • Saving a Trace
• Viewer Display
  • 3.1 Window Management
  • 3.2 Waveform View
    • 3.2.1 Clock Position Selection
    • 3.2.2 Data View Pane
    • 3.2.3 Viewport Slider in Navigation Bar
    • 3.2.4 Snap to Edge
    • 3.2.5 Placing Cursors
    • 3.2.6 Zoom In and Zoom Out
    • 3.2.7 Overlay Signals Mode
    • 3.2.8 Zoom Box
    • 3.2.9 Signal Names Context Sensitive Menu
    • 3.2.10 Context Sensitive Menu
    • 3.2.11 Choosing Chip Select Color Highlighting
    • 3.2.12 Timing and Protocol Violations
    • 3.2.13 Right-Click Functionality in Waveform View
      • Go to Next Gap
      • Goes to the next gap (see See “Gap Markers” on page 131).
      • Go to Previous Gap
      • Go to Marker
      • Go to Cursor
      • Go to Trigger
      • Go to Time
      • Go to Selection
      • Set New Marker
      • Set and Edit New Marker
      • Place Marker
      • Edit This Marker
      • Edit Marker
      • Go to Next Transition [Alert]
      • Go to Previous Transition [Alert]
      • Delete This Marker
      • Delete Marker
      • Delete All Markers
      • Add Lines
      • Delete Line [Alert]
      • Show/Hide Sub Signals
      • Preferences
    • 3.2.14 Markers
      • Creating Markers
      • Signal Names Column
      • Cursors
  • 3.3 Viewport Slider/Navigation Bar
    • 3.3.1 Traces Captured with Filtering Enabled
    • 3.3.2 Gap Markers
  • 3.4 Listing View
  • 3.5 Bank State View
    • 3.5.1 Supported States in the Bank View State
      • Legend Display
      • Active States
      • Configuring Visible Banks
      • Common Features of Bank State View and Waveform View
    • 3.5.2 Views
      • Maximum Zoomed In View
      • Default Zoom Level
      • Maximum Zoomed Out View
  • 3.6 Traffic Summary
    • Traffic Summary - Toolbar Tools
    • Traffic Summary - Commands
    • Traffic Summary - Performance
    • Traffic Summary - Violations
  • 3.7 Timing Calculator View
  • 3.8 Last MRS Values
  • 3.9 Row Usage Report
    • Defining Target Row(s)
    • Define Analysis Detail Parameters
    • Define Report Boundary
    • Cyclic Row Usage Report
  • 3.10 Timing Violation Reanalysis
• Real Time Statistics
  • 4.1 Devices Dashboard
  • 4.2 Real-Time Statistics View
    • 4.2.1 Command Statistics
    • 4.2.2 Last MRS Values
    • 4.2.3 Real-Time Statistics Buttons
    • 4.2.4 RTS Preferences
    • 4.2.5 RTS Print
• Application Note
  • 5.1 DDR3 and DDR4 JEDEC Timing Violations Summary
    • 5.1.1 V01 - tRAS ACTIVATE to PRECHARGE command period (Min)
    • 5.1.2 V02 - tRAS ACTIVATE to PRECHARGE command period (Max)
    • 5.1.3 V03 - tRRD ACTIVATE to ACTIVATE command period (DDR3 different bank, same rank) (DDR4 - same bank group)
    • 5.1.4 V04 - tFAW Four Activate Window
    • 5.1.5 V05 - tRCDx ACTIVATE to internal read or write delay (same bank)
    • 5.1.6 V06 - tWTP WRITE to PRECHARGE delay
    • 5.1.7 V07 - tRTPx READ to PRECHARGE delay
    • 5.1.8 V08 - tRP PRECHARGE to a Valid Command
    • 5.1.9 V09 - tWRA WRA to a Valid Command
    • 5.1.10 V10 - t RFC REFRESH to a Valid Command
    • 5.1.11 V11 - tREFI REFRESH Interval
    • 5.1.12 V12 - tRTR READ to READ delay (DDR3 - same rank) (DDR4 - same bank group)
    • 5.1.13 V13 - tdrRTR READ to READ delay (different rank - same DIMM)
    • 5.1.14 V14 - tddRTR READ to READ delay (different DIMM)
    • 5.1.15 V15 - tRTW READ to WRITE delay (same rank)
    • 5.1.16 V16 - tdrRTW READ to WRITE delay (different rank, same DIMM)
    • 5.1.17 V17 - tddRTW READ to WRITE delay (different DIMM)
    • 5.1.18 V18 - tWTR WRITE to READ delay ( DDR3 - same rank) (DDR4 - same bank group)
    • 5.1.19 V19 - tdrWTR WRITE to READ delay (different rank, same DIMM)
    • 5.1.20 V20 - tddWTR WRITE to READ delay (different DIMM)
    • 5.1.21 V21 - tWTW WRITE to WRITE delay ( DDR3 - same rank) (DDR4 - same bank group)
    • 5.1.22 V22 - tddWTW WRITE to WRITE delay (different rank, same DIMM)
    • 5.1.23 V23 - tddWTW WRITE to WRITE delay (different DIMM)
    • 5.1.24 V24 - tXS SELF REFRESH EXIT to a Valid Command (without DLL)
    • 5.1.25 V25 - tXSDLL SELF REFRESH EXIT to a Valid Command (with DLL)
    • 5.1.26 V26 - tCKESR SELF REFRESH ENTRANCE to SELF REFRESH EXIT
    • 5.1.27 V27 - tACTPDEN ACTIVE to POWER DOWN ENTRY
    • 5.1.28 V28 - REFPDEN REFRESH to POWER DOWN ENTRY
    • 5.1.29 V30 - tPRPDEN PRECHARGE / PRECHARGE ALL to POWER DOWN ENTRY
    • 5.1.30 V31 - tRDPDEN READ / READ AUTO to POWER DOWN ENTRY
    • 5.1.31 V32 - tWRPDEN WRITE to POWER DOWN ENTRY
    • 5.1.32 V33 - tWRAPDEN WRITE AUTO to POWER DOWN ENTRY
    • 5.1.33 V34 - tXP POWER DOWN EXIT to a Valid Command without DLL
    • 5.1.34 V35 - tXPDLL POWER DOWN EXIT to a Valid Command with DLL - DDR3
    • 5.1.35 V36 - tCKE Clock Enable minimum pulse width
    • 5.1.36 V37 - tPD POWER DOWN ENTRY to POWER DOWN EXIT
    • 5.1.37 V38 - tZQCS SHORT Calibration Sequence to a Valid Command
    • 5.1.38 V39 - tZQOper ZQCL to a Valid Command
    • 5.1.39 V40 - tZQinit First ZQCL after Reset to a Valid Command
    • 5.1.40 V41 - tMRD MODE Register Set to Mode Register Set
    • 5.1.41 V42 - tMOD Mode Register Set Command to a Valid Command
    • 5.1.42 V43 - tXPR First Clock Enable High after Reset to MRS
    • 5.1.43 V44 - CCD-S Read to Read Delay (short) Different bank group, same rank DDR4
    • 5.1.44 V45 - tWTW-DBG Write to Write Delay (short) Different bank group; same rank -DDR4
    • 5.1.45 V46 - tWTR- DBG Write to Read Delay (short) Different bank group; same rank DDR4
    • 5.1.46 V47 - tRRD-S Activate to Activate Delay (short) Different bank group; same rank DDR4
    • 5.1.47 V48 - tXS-FAST SRX to a Valid Command with DLL - DDR4
  • 5.2 Supplemental Timing Information
    • 5.2.1 tWR WR (write recovery for auto-precharge)
• China Restriction of Hazardous Substances Table
• How to Contact Teledyne LeCroy
• Index