FUJITSU MHW2120BS User Manual
Page 186
Interface
*13 WORD 78
Bits 15-7: Reserved
Bit 6:
'1' = Supports the software settings preservation.
Bit 5:
Reserved
Bit 4:
'1'= Supports the in-order data delivery.
Bit 3:
'1'= Supports the Power Management initiation from the device to
the host system.
Bit 2:
'1' = Supports the DMA Setup FIS Auto-Activate optimization.
Bit 1:
'1' = Supports the non-zero buffer offset in the DMA Setup FIS.
Bit 0:
Reserved
*14 WORD 79
Bits 15-7: Reserved
Bit 6:
'1' = Enables the software settings preservation.
Bit 5:
Reserved
Bit 4:
'1' = Enables the in-order data delivery.
Bit 3:
'1' = Enables the Power Management initiation function from Bit 2:
'1' = Enables the Auto-Activate optimization function in the DMA
Setup FIS.
Bit 1:
'1' = Enables the non-zero buffer offset function in the DMA
Setup FIS.
Bit 0:
Reserved
*15 WORD 80
Bits 15-9: Reserved
Bit 8:
'1' = ATA/ATAPI-8 ACS/ST supported
Bit 7:
'1' = ATA/ATAPI-7 supported
Bit 6:
'1' = ATA/ATAPI-6 supported
Bit 5:
'1' = ATA/ATAPI-5 supported
Bit 4:
'1' = ATA/ATAPI-4 supported
Bit 3:
'1' = ATA-3 supported
Bit 2:
'1' = ATA-2 supported
Bits 1-0: Undefined
5-112
C141-E249