Document Outline

• Cover
• Copy right
• Revision History
• Preface
• Important Alert Items
• Manual Organization
• Contents
• Illustrations
• CHAPTER 1 Device Overview
  • 1.1 Features
    • 1.1.1 Functions and performance
    • 1.1.2 Adaptability
    • 1.1.3 Interface
  • 1.2 Device Specifications
    • 1.2.1 Specifications summary
    • 1.2.2 Model and product number
  • 1.3 Power Requirements
  • 1.4 Environmental Specifications
  • 1.5 Acoustic Noise
  • 1.6 Shock and Vibration
  • 1.7 Reliability
  • 1.8 Error Rate
  • 1.9 Media Defects
• CHAPTER 2 Device Configuration
  • 2.1 Device Configuration
  • 2.2 System Configuration
    • 2.2.1 ATA interface
    • 2.2.2 1 drive connection
    • 2.2.3 2 drives connection
• CHAPTER 3 Installation Conditions
  • 3.1 Dimensions
  • 3.2 Mounting
  • 3.3 Cable Connections
    • 3.3.1 Device connector
    • 3.3.2 Cable connector specifications
    • 3.3.3 Device connection
    • 3.3.4 Power supply connector (CN1)
  • 3.4 Jumper Settings
    • 3.4.1 Location of setting jumpers
    • 3.4.2 Factory default setting
    • 3.4.3 Master drive-slave drive setting
    • 3.4.4 CSEL setting
• CHAPTER 4 Theory of Device Operation
  • 4.1 Outline
  • 4.2 Subassemblies
    • 4.2.1 Disk
    • 4.2.2 Head
    • 4.2.3 Spindle
    • 4.2.4 Actuator
    • 4.2.5 Air filter
  • 4.3 Circuit Configuration
  • 4.4 Power-on Sequence
  • 4.5 Self-calibration
    • 4.5.1 Self-calibration contents
    • 4.5.2 Execution timing of self-calibration
    • 4.5.3 Command processing during self-calibration
  • 4.6 Read/write Circuit
    • 4.6.1 Read/write preamplifier (HDIC)
    • 4.6.2 Write circuit
    • 4.6.3 Read circuit
    • 4.6.4 Digital PLL circuit
  • 4.7 Servo Control
    • 4.7.1 Servo control circuit
    • 4.7.2 Data-surface servo format
    • 4.7.3 Servo frame format
    • 4.7.4 Actuator motor control
    • 4.7.5 Spindle motor control
• CHAPTER 5 Interface
  • 5.1 Physical Interface
    • 5.1.1 Interface signals
    • 5.1.2 Signal assignment on the connector
  • 5.2 Logical Interface
    • 5.2.1 I/O registers
    • 5.2.2 Command block registers
    • 5.2.3 Control block registers
  • 5.3 Host Commands
    • 5.3.1 Command code and parameters
    • 5.3.2 Command descriptions
    • 5.3.3 Error posting
  • 5.4 Command Protocol
    • 5.4.1 Data transferring commands from device to host
    • 5.4.2 Data transferring commands from host to device
    • 5.4.3 Commands without data transfer
    • 5.4.4 Other commands
    • 5.4.5 DMA data transfer commands
  • 5.5 Ultra DMA Feature Set
    • 5.5.1 Overview
    • 5.5.2 Phases of operation
      • 5.5.2.1 Ultra DMA burst initiation phase
      • 5.5.2.2 Data transfer phase
      • 5.5.2.3 Ultra DMA burst termination phase
    • 5.5.3 Ultra DMA data in commands
      • 5.5.3.1 Initiating an Ultra DMA data in burst
      • 5.5.3.2 The data in transfer
      • 5.5.3.3 Pausing an Ultra DMA data in burst
      • 5.5.3.4 Terminating an Ultra DMA data in burst
    • 5.5.4 Ultra DMA data out commands
      • 5.5.4.1 Initiating an Ultra DMA data out burst
      • 5.5.4.2 The data out transfer
      • 5.5.4.3 Pausing an Ultra DMA data out burst
      • 5.5.4.4 Terminating an Ultra DMA data out burst
    • 5.5.5 Ultra DMA CRC rules
    • 5.5.6 Series termination required for Ultra DMA Series termination resistors are required
  • 5.6 Timing
    • 5.6.1 PIO data transfer
    • 5.6.2 Multiword DMA data transfer
    • 5.6.3 Transfer of Ultra DMA data
      • 5.6.3.1 Starting of Ultra DMA data In Burst
      • 5.6.3.2 Ultra DMA data burst timing requirements
      • 5.6.3.3 Sustained Ultra DMA data in burst
      • 5.6.3.4 Host pausing an Ultra DMA data in burst
      • 5.6.3.5 Device terminating an Ultra DMA data in burst
      • 5.6.3.6 Host terminating an Ultra DMA data in burst
      • 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings
      • 5.6.3.8 Sustained Ultra DMA data out burst
      • 5.6.3.9 Device pausing an Ultra DMA data out burst
      • 5.6.3.10 Host terminating an Ultra DMA data out burst
      • 5.6.3.11 Device terminating an Ultra DMA data in burst
    • 5.6.4 Power-on and reset
• CHAPTER 6 Operations
  • 6.1 Device Response to the Reset
    • 6.1.1 Response to power-on
    • 6.1.2 Response to hardware reset
    • 6.1.3 Response to software reset
    • 6.1.4 Response to diagnostic command
  • 6.2 Address Translation
    • 6.2.1 Default parameters
    • 6.2.2 Logical address
  • 6.3 Power Save
    • 6.3.1 Power save mode
    • 6.3.2 Power commands
  • 6.4 Defect Management
    • 6.4.1 Spare area
    • 6.4.2 Alternating defective sectors
  • 6.5 Read-Ahead Cache
    • 6.5.1 Data buffer configuration
    • 6.5.2 Caching operation
    • 6.5.3 Usage of read segment
      • 6.5.3.1 Mis-hit (no hit)
      • 6.5.3.2 Sequential read
      • 6.5.3.3 Full hit (hit all)
      • 6.5.3.4 Partially hit
    • 6.6 Write Cache
• Glossary
• Acronyms and Abbreviations
• Comment Form
• Back