Motorola MVME172 - Manual (Page 189)

3-1
3
3 MC2 Chip
Introduction
The Memory Controller ASIC (MC2 chip) is one of three ASICs that are
part of the MVME172 hardware set.
Summary of Major Features
❏ BBRAM and time-of-day clock (M48T58) interface with bus
sizing.
❏ PROM interface with bus sizing.
❏ Flash interface with bus sizing.
❏ SRAM controller supporting several configurations.
❏ DRAM controller supporting several configurations.
❏ Four Zilog serial interfaces implemented with Z85230 SCC device.
❏ NCR 53C710 SCSI Coprocessor interface.
❏ Intel 82596CA LAN Coprocessor interface.
❏ Four 32-bit tick timers.
❏ Interrupt support for ABORT switch, LAN, SCSI, SCC, DRAM,
and Timers.
❏ Local bus access timer.
❏ Watchdog timer.