Dram control register, Dram control register -45 – Motorola MVME172 User Manual
Page 233
Programming Model
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3-45
3
signal is sent to the local bus. Note that the Version
Register bit V1 must be set to a 1 to enable the MC2 chip
access timer (i.e., it must be a "No VMEbus Interface"
option).
0
8
µ
s
1
64
µ
s
2
256
µ
s
3
The timer is disabled.
DRAM Control Register
This register controls the parity checking mode and DRAM enable for
non-ECC applications.
RAMEN
This bit enables the access of the DRAM. The DRAM
should be enabled after the DRAM Space Base Address
Register is enabled and the ROM0 bit has been cleared.
The DRAM Space Base Address Register is located at
$FFF42020 bits 31 - 16 and the ROM0 bit is located at
$FFF42040 bit 20.
ADR/SIZ
$FFF42048 (8 bits)
BIT
31
30
29
28
27
26
25
24
NAME
WWP
PARINT
PAREN
RAMEN
OPER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0
0
0
0
0 PL
0 PL
0 PL
0 PL