Marantz SUPER AUDIO CD PLAYER SA8400 User Manual
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3-7
No. Pin Name
I/O Functions
1 VSC
-
It fi xed to ground.( for Core)
2 XMSLAT
I
Latch input for mCOM serial communication.
3 MSCK
I
Shift clock input for mCOM serial communication.
4 MSDATI
I
Data input for mCOM serial communication.
5 VDC
-
+2.5V Power for Core.
6 MSDATO
O
Data output for mCOM serial communication. "Hi-Z" potential except the output mode.
7 MSREADY
O
Completion fl ag of output preparation for mCOM serial communication. "L" is outputted at the time of completion.
8 XMSDOE
O
Output enable pin for mCOM serial communication. "L" is outputted at the time of MSDATO mode.
9 XRST
I
Reset pin. The whole IC is reset by at the time of "L" potential.
10 SMUTE
Ipd Soft Mute. Soft mute of the audio output is carried out at the time of "H" potential.It releases at the time of "L"
potential.
11 MCKI
I
Master Clock input.
12 VSIO
-
It fi xed to Ground. Ground for I/O.
13 EXCKO1
O
External output Clock 1.
14 EXCKO2
O
External output Clock 2.
15 LRCK
O
44.1kHz, 1Fs Clock output.
16 FRAME
O
Frame signal output.
17 VDIO
-
+3.3V Power for I/O.
18 MNT0
O
Monitor output.
19 MNT1
O
Monitor output.
20 MNT2
O
Monitor output.
21 MNT3
O
Monitor output.
22 TESTO
O
Output terminal for a Test. (open)
23 TESTO
O
Output terminal for a Test.(open)
24 TESTO
O
Output terminal for a Test.(open)
25 TESTO
O
Output terminal for a Test.(open)
26 TCK
I
Clock input for a Test. It fi xed to "L" potential.
27 TDI
Ipu Input pin(pull-up) for a Test.(open)
28 VSC
-
It fi xed to Ground. Ground for CORE.
29 TDO
O
Output for a Test.(open).
30 TMS
Ipu Input pin(pull-up) for a Test.(open)
31 TRST
Ipu Reset pin(pull-up) for a Test. Input the Power-on reset signal or fi xed to "L" potential.
32 TEST1
I
Test input pin. It fi xed to "L" potential.
33 TEST2
I
Test input pin. It fi xed to "L" potential.
34 TEST3
I
Test input pin. It fi xed to "L" potential.
35 VDC
-
+2.5V Power for CORE.
36 TESTO
O
Out put for TEST. It fi xed to open.
37 XBIT
O
DST monitor.
38 SUPDT0
O
Supplementary data output. (LSB)
39 SUPDT1
O
Supplementary data output.
40 SUPDT2
O
Supplementary data output.
41 SUPDT3
O
Supplementary data output.
42 VSIO
-
Ground for I/O.
43 SUPDT4
O
Supplementary data output.
44 SUPDT5
O
Supplementary data output.
45 VDIO
-
+3.3V Power for I/O.
46 SUPDT6
O
Supplementary data output.
47 SUPDT7
O
Supplementary data output. (MSB)
48 XSUPAK
O
Supplementary data Acknowledge output terminal.
49 VSC
-
Ground for CORE.
50 TESTO
O
Output for TEST. (open)
51 TESTI
I
Input for TEST. It fi xed to "L" potential.
52 TESTI
I
Input for TEST. It fi xed to "L" potential.
53 TESTO
O
Output for TEST. (open)
54 VDC
-
+2.5V Power for CORE.
55 DSADML
O
DSD Data output terminal for Lch Down Mix.
56 DSADMR
O
DSD Data output terminal for Rch Down Mix.
57 BCKASL
I
I/O selection terminal of the Bit clock for DSD data output. L=input (Slave), H=output (Master)
58 VSDSD
-
Ground terminal for DSD data output.
59 BCKAI
I
Bit clock input terminal for DSD data output. Input a Bit clock into this terminal at the time of BCKASL="L"
potential.
60 BCKAO
O
Bit clock output terminal for DSD data output. Bit clock output from this terminal at the time of BCKASL="H"
potential.
61 PHREFI
I
Reference phase signal input terminal for DSD output phase modulation.
62 PHREFO
O
Reference phase signal output terminal for DSD output phase modulation.
IC401 : CXD2753R