IBM POWERPC 750GL - Manual (Page 356)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Performance Monitor and System Related Features
Page 356 of 377
gx_11.fm.(1.2)
March 27, 2006
11.4 Event Selection
Event selection is handled through MMCR0 and MMCR1.
• The four event-select fields in MMCR0 and MMCR1 are:
– MMCR0[19:25] PMC1SELECT PMC1 input selector. 128 events selectable; 25 defined. See
Table 11-2 on page 352.
– MMCR0[26:31] PMC2SELECT PMC2 input selector. 64 events selectable; 21 defined. See
Table 11-3 on page 352.
– MMCR0[0:4] PMC3SELECT PMC3 input selector. 32 events selectable and defined. See
Table 11-4 on page 353.
– MMCR0[5:9] PMC4SELECT PMC4 input selector. 32 events selectable. See Table 11-5 on
page 354.
• In the tables, a correlation is established between each counter, events to be traced, and the pattern
required for the desired selection.
• The first five events are common to all four counters and are considered to be reference events. These
are as follows.
– 00000 Register holds current value
– 00001 Number of processor cycles
– 00010 Number of completed instructions, not including folded branches
– 00011 Number of transitions from 0 to 1 of specified bits in the Time Base Lower (TBL) register.
Bits are specified through RTCSELECT, MMCR0[7–8].
00 = 31
01 = 23
10 = 19
11 = 15
– 00100 Number of instructions dispatched. 0, 1, or 2 per cycle
• Some events can have multiple occurrences per cycle, and therefore need two or three bits to represent
them.
11.5 Notes
The following warnings should be noted:
• Only those load and stores in queue position 0 of their respective load/store queues are monitored when
a threshold event is selected in PMC1.
• The 750GX cannot accurately track threshold events with respect to the following types of loads and
stores:
– Unaligned load-and-store operations that cross a word boundary
– Load-and-store multiple operations
– Load-and-store string operations