IBM X3650 M3 - Manual (Page 6)

Leadership enterprise server with significantly lower cost of ownership in a highly available and
expandable, rack-dense, 2U dual-socket server
Please see the Legal Information section for important notices and information.
6
slots (192GB in 12 slots, as of 2Q/2010), or up to 24GB of UDIMM (unbuffered DIMM) memory in
12 slots (48GB in 12 slots, as of 2Q/2010). The x3650 M3 also supports either standard 1.5V
DIMMs, or 1.35V DIMMs that consume 10% less energy. Redesign in the architecture of the
Xeon 5500 and 5600 series processors bring radical changes in the way memory works in these
servers. For example, the Xeon 5500 and 5600 series processors integrate the memory
controller inside the processor, resulting in two memory controllers in a 2-socket system. Each
memory controller has three memory channels. Depending on the type of memory, population of
memory, and processor model, the memory may be clocked at 1333MHz, 1066MHz or 800MHz.
Notes: In the example above, with two processors installed, if one DIMM per channel is to be
installed, follow the numbering in light blue. For two DIMMs per channel, use blue and yellow. If
only one processor is installed, only the first nine DIMM slots can be used. Adding a second
processor not only doubles the amount of memory available for use, but also doubles the number
of memory controllers, thus doubling the system memory bandwidth. If you add a second
processor, but no additional memory for the second processor, the second processor would have
to access the memory from the first processor “remotely,” resulting in longer latencies and lower
performance. The latency to access remote memory is almost 75% higher than local memory
access. So, the goal should be to always populate both processors with memory.
The X55xx, L5640, and X56xx processor models support up to 1333MHz memory clock speed.
With new single-rank and dual-rank RDIMMs and UDIMMs, L5640 and X56xx processors support
2 DIMMs per channel (2DPC) at 1333MHz; X55xx processors can support 2DPC at 1333MHz via
the special bid process, otherwise 2DPC will drop the memory access rate to 1066MHz. The
E552x/E562x-and-up and L56xx models support a maximum of 1066MHz clock speed (and thus
memory access rate), and the E550x models support 800MHz clock speed.
Using 1333MHz memory (where supported) versus 1066MHz offers up to 9% better
performance, while 1066MHz memory produces up to 28% better performance than 800MHz
memory. Xeon 5550/5600 Series processors access memory with almost 50% lower latency
than the earlier 5400 Series processors. That can result in faster processing of latency-sensitive
workloads.
Regardless of memory speed, the Xeon 5500/5600 platform represents a significant improvement
in memory bandwidth over the previous Xeon 5400 platform. At 1333MHz, the improvement is
almost 500% over the previous generation. This huge improvement is mainly due to the dual
integrated memory controllers and faster DDR3 1333MHz memory. Throughput at 800MHz is 25
gigabytes per second (GBps); at 1066MHz it’s 32GBps; and at 1333MHz it’s 35GBps. This
improvement translates into improved application performance and scalability.
Memory interleaving refers to how physical memory is interleaved across the physical DIMMs. A
balanced system provides the best interleaving. A Xeon 5500/5600 processor-based system is
balanced when all memory channels on a socket have the same amount of memory.
The 5500 and 5600 Series processors support single-, dual-, and quad-rank memory. A memory
rank is simply a segment of memory that is addressed by a specific address bit.
• A typical memory DIMM description is 4GB 2Rx4 DIMM
• The 2R designator is the rank count for this particular DIMM (2R = dual-rank)
• The x4 designator is the data width of the rank
It is important to ensure that DIMMs with the appropriate number of ranks are populated in each
channel for optimal performance. Whenever possible, use dual-rank DIMMs in the system. Dual-
rank DIMMs offer better interleaving and hence better performance than single-rank DIMMs. For
1-18: DIMM population sequence , D1-D18: DIMM slot assignments
1333MHz
Xeon 5500 / 5600 Processor 0 Xeon 5500 / 5600 Processor 0
CH0
800MHz
QPI QPI
1
11
15 13
7 9
5 3
D2
D1 D4
D3
D5
D6
D8
D9
2
12
16 14
8 10
6 4
D11
D10 D13
D12
D14
D15
D17
D18
CH1 CH2 CH0 CH1 CH2
Memory Controller Memory Controller
17
D7
18
D16
Xeon 5500 / 5600 Processor 1 Xeon 5500 / 5600 Processor 1
1066MHz
L5640 & X5600 series
support
2DPC@1333MHz
X5500 series support
2DPC@1333MHz
by Special Bid
1333MHz
Xeon 5500 / 5600 Processor 0 Xeon 5500 / 5600 Processor 0
CH0
800MHz
QPI QPI
1
11
15 13
7 9
5 3
D2
D1 D4
D3
D5
D6
D8
D9
2
12
16 14
8 10
6 4
D11
D10 D13
D12
D14
D15
D17
D18
CH1 CH2 CH0 CH1 CH2
Memory Controller Memory Controller
17
D7
18
D16
Xeon 5500 / 5600 Processor 1 Xeon 5500 / 5600 Processor 1
1066MHz
L5640 & X5600 series
support
2DPC@1333MHz
X5500 series support
2DPC@1333MHz
by Special Bid