Intel 80303 - Manual (Page 15)

Intel ® 80303 and 80302 I/O Processors Specification Update 15
Specification Clarifications
Specification Clarifications
1. ECC is Always Enabled
Problem: ECC is always enabled, therefore do not design an Intel® 80303 I/O processor based product
without ECC implemented, this causes severe system errors. On the Intel® 80960RM/RN I/O
processors, ECCR.3 can be cleared to disable ECC, but with the 80303 I/O processor, ECCR.3 is
reserved.
2. 32-bit SDRAM is Not Supported
Problem: The memory controller on the 80303 I/O processor supports between 32 and 512 Mbytes of 64-bit
SDRAM, but 32-bit SDRAM is not supported. On the 80960RM/RN I/O processors, 32-bit
memory was selected by the 32BITMEM_EN# pin (multiplexed on RAD[2]), and by reading a '0'
from SDCR.2, this would indicate a 32-bit data bus width. But, for the 80303 I/O processor the
32BITMEM_EN# pin does not exist and SDCR.2 is reserved.
3. Non-Battery Backup Systems
Problem: Applications that do not support battery back-up should follow these recommendations:
1. Pull the PWRDELAY pin low through a 1.5K pulldown. Pulling it low has the effect of
keeping the power fail state machine in reset, therefore not allowing the power fail sequence to
ever occur.
2. Pull the CKE pins high on the SDRAMs, and leave the SCKE signals on the 80303 as 'no
connects'. This keeps the SDRAM from entering a pseudo, self-refresh mode which can cause
a lock-up condition on the SDRAM device.
4. POCCDR and SOCCDR Functionality
Problem: The Primary Outbound Configuration Cycle Data Register (POCCDR) and Secondary Outbound
Configuration Cycle Data Register (SOCCDR) are used to initiate configuration cycles to PCI
target devices. On page 15-57, Table 15-26 in the Intel
®
80303 I/O Processor Developer’s Manual,
these registers are stated as “Not Available in PCI Configuration Space”.
To clarify, when these registers are either read or written via PCI during a scan of configuration space,
an unwanted configuration cycle is initiated by the 80303 to the address held in the Primary
Outbound Configuration Cycle Address Register (POCCAR) or Secondary Outbound Configuration
Cycle Address Register (SOCCAR) based on a read or write to POCCDR or SOCCDR respectively.
An invalid address causes the 80303 to signal a master abort. Only the first 64 bytes in the ATU
Configuration Header is read during configuration. Any thing above 64 bytes up to 256 bytes is
defined as device-specific and not accessed by a master. This does not have to rule out access by any
master, only a master which does not have knowledge of the device-specific registers.
5. ‘Bus Hold’ Devices on the RAD Bus
Problem: There are six user mode configuration pins (RST_MODE#, ONCE#, STEST, RETRY, SPMEM#
and 32BITPCI_EN#) and three test mode configuration pins (on RAD8, 7 and 0) that are
multiplexed on the RAD[8:0] signals. All these signals have internal pull-ups, so there is no need
for external pull-ups. But, if the application requires an active low signal, then an external
pull-down needs to be added. The configuration signals are latched on the rising edge of P_RST#.
Devices with a ‘bus hold’ feature (i.e., CPLD) connected to the RAD bus may pull the RAD[8:0]
signals low at the rising edge of P_RST#, causing the 80303 to enter an undesired mode. 80303
designs that use ‘bus hold’ devices should either turn off the ‘bus hold’ feature or verify that proper
signal levels are being maintained at the rising edge of P_RST#.