Document Outline

• Contents
  • Unpacking and Special Handling Instructions
  • Revision History
  • Three Year Limited Warranty
  • 1.0 ICP-PIII CPU
  • 1.01 Interfacing
  • 1.02 Peripherals
  • 1.03 Software
  • 1.04 Graphics
  • 1.1 Specifications
  • 1.2 Configuration
  • Table 1.20 ‘Processor Overview
  • Figure 1.20 ICP-PIII Overview
  • 1.3 Software
  • 1.31 Linux
  • 1.32 VentureCom
  • 1.33 Windows 2000
  • 1.34 Windows CE
  • 1.35 VxWorks
  • 1.36 OS-9 x86
  • 1.37 QNX
  • 1.38 Jbed
  • 1.4 Hardware
  • 1.41 Block Diagram
  • Figure 1.41 Block Diagram
  • 1.42 Connector Location
  • Figure 1.42 Connector Locations
  • 1.43 Connector Description
  • Table 1.43 Connector Description
  • Table 1.43 Continued
  • 1.44 Front-Panel Features
  • Table 1.44 Front Panels
  • Figure 1.44 Front-Panel Options
  • 1.45 Interface Positions
  • Figure 1.45 Interfaces
  • 2.0 Memory Map
  • Figure 2.00 System Architecture
  • Table 2.00 UMB Reservations for ISA
  • Table 2.01 Port Addressing
  • 2.1 I/O Mapped Peripherals
  • Table 2.10 Legacy I/O Map (ISA Compatible)
  • 2.2 Memory Mapped Peripherals
  • 2.3 Interrupt Routing
  • Table 2.30 PC-AT Interrupt Definitions
  • 2.4 Inova PIII Device List
  • Table 2.40 Legacy I/O Map (ISA Compatible)
  • 2.5 Interrupt Configuration
  • Table 2.50 CompactPCI Bus Interrupts
  • 2.6 Timer / Counter
  • 2.7 Watchdog
  • 3.0 CompactPCI J1/J2 Connector
  • 3.01 CompactPCI Connector
  • Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector
  • 3.02 ICP-PIII Connector J1 and J2
  • Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment
  • Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard)
  • Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)
  • Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)
  • Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C)
  • Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration
  • 3.1 CompactPCI Backplane
  • Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot
  • 3.2 Interfaces
  • 3.21 J7 & J12 Fast Ethernet
  • Figure 3.21 RJ45 Pinout
  • Table 3.21 Ethernet Connector Signals
  • 3.22 J17 VGA Interface
  • Figure 3.22 High-Density D-Sub VGA Interface Pinout
  • Table 3.22 Video Output Connector Signals
  • Table 3.22b Video Resolutions
  • 3.23 J16 PanelLink Interface
  • Figure 3.23 PanelLink Interface Connector
  • Table 2.12 PanelLink Interface
  • 2.24 J16 GigaSTAR Interface
  • Figure 2.24 GigaSTAR D-Sub Interface Pinout
  • Table 2.11 GigaSTAR Interface
  • 3.25 J19 USB Interface
  • Figure 3.25 USB Interface Pinout
  • Table 3.25 USB Connector Signals
  • 3.26 J15 FireWire Interface
  • Figure 3.26 FireWire Interface Pinout
  • Table 3.26 FireWire Connector Signals
  • 3.27 J20 Infrared (iRdA) Interface
  • 3.28 J20 Reset Button
  • 3.29 J14 FLASH Interface
  • 3.30 J18 Floppy Disk Interface
  • 3.31 Connecting the PIII to the Inova IPB-FPE8
  • Figure 3.31 CPU to IPB-FPE8 Connection
  • 3.32 Connecting the PIII to the Inova ICP-HD-1
  • Figure 3.32 CPU to ICP-HD-1 Connection
  • 3.33 Connecting the PIII to the Inova IPB-FPE12
  • Figure 3.33 CPU to IPB-FPE12 Connection
  • 3.34 Connecting the PIII to the Inova IPB-FPE12
  • Figure 3.34 CPU to IPB-FPE12 Connection
  • 3.35 Connecting the PIII to the ICP-FD-1
  • Figure 3.35 CPU to Slim-Line Floppy Disk Connection
  • A1 IPB-FPE8 CPU Extension
  • A1.1 J11 Interface for COM1, Mouse & Keyboard
  • A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)
  • Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU
  • A1.3 Stand-Alone IPB-FPE8
  • Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8
  • A1.4 IPB-FPE8MS (Theme Variation)
  • Figure A1.4 Piggyback Interface IPB-FPE8MS
  • Table A1.4 IPB-FPE8MS Connector Description
  • A1.5 IPB-FPE8MS Description
  • Figure A1.5 Top & Bottom Views of the IPB-FPE8MS
  • Table A1.5 Standard Hard-Disk & Floppy Disk Connectors
  • A1.6 Keyboard Interface
  • Figure A1.6 Keyboard Interface Pinout
  • Table A1.6 Keyboard Connector Signals
  • A1.7 Mouse Interface
  • Figure A1.7 Mouse Interface Pinout
  • Table A1.7 Mouse Connector Signals
  • A1.8 COM1 Interface
  • Figure A1.8 COM1 Interface Pinout
  • Table A1.8 COM1 Connector Signals
  • B1 ICP-HD CPU Extension
  • B1.1 J11, J13 Interfaces
  • B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)
  • Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU
  • B1.3 IDE Carrier Board ICP-HD-1
  • Figure B1.3 IDE Carrier Board ICP-HD1
  • Table B1.3 ICP-HD-1 Connector Description
  • B1.4 ICP-HDE8MS (Theme Variation)
  • Figure B1.4 IDE Carrier ICP-HDE8MS
  • Table B1.4 IPB-HDE8MS Connector Description
  • B1.5 ICP-HDE8MS Description
  • Figure B1.5 Top & Bottom Views of the ICP-HDE8MS
  • B1.6 Keyboard Interface
  • Figure B1.6 Keyboard Interface Pinout
  • Table B1.6 Keyboard Connector Signals
  • B1.7 Mouse Interface
  • Figure B1.7 Mouse Interface Pinout
  • Table B1.7 Mouse Connector Signals
  • B1.8 COM1 & COM 2 Interfaces
  • Figure B1.8 COM1 & COM2 Interface Pinout
  • Table B1.8 COM1 & COM2 Connector Signals
  • B1 IPM-ATA CPU Extension
  • B1.1 J1 Interfaces
  • Figure B1.1a Dedicated IPM-ATA Backplane
  • B1.1 J1 Interfaces (Contd.)
  • Figure B1.1b The Complete Connection Picture
  • B1.2 IPM-ATA-HD
  • Figure B1.2 IPM-ATA-HD Board Layout
  • Table B1.2 IPM-ATA-HD Jumper Description
  • B1.3 IPM-ATA-CF
  • Figure B1.3 IPM-ATA-CF Board Layout
  • Table B1.3 IPM-ATA-CF Jumper Description
  • B1.4 IPM-ATA-PCMCIA
  • Figure B1.4 IPM-ATA-PCMCIA Board Layout
  • Table B1.4 IPM-ATA-PCMCIA Jumper Description
  • B1.5 Device Compatibility
  • Table B1.5 Compatibility List
  • C1 IPB-FPE12 CPU Extension
  • C1.1 J13 Interface for LPT1 & COM2
  • C1.2 IPB-FPE12 & Front-panel (4HP or 12HP)
  • Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU
  • C1.3 LPT1 & COM2 Piggyback
  • Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12
  • Table C1.3 IPB-FPE12 Connector Description
  • C1.4 LPT1 Interface
  • Figure C1.6 LPT1 Interface Pinout
  • Table C1.6 LPT1 Connector Signals
  • C1.5 COM2 Interface
  • Figure C1.5 COM2 Interface Pinout
  • Table C1.5 COM2 Connector Signals
  • D1 IPB-RIO CPU Extension
  • D1.1 IPB-RIO-HD-FD
  • Figure D1.1 IPB-RIO-HD-FD
  • D1.2 IPB-RIO-HD-LPT-(FLEX)
  • Figure D1.2 IPB-RIO-HD-LPT-(FLEX)
  • D1.3 IPB-RIO-C-SHORT
  • Figure D1.3 IPB-RIO-C-SHORT
  • Table D1.3 Rear I/O Type ‘C’
  • D1.4 IPB-RIO-C-80MM
  • Figure D1.4 IPB-RIO-C-80MM
• Overview Contents
  • 1.0 ICP-PIII CPU
  • 1.01 Interfacing
  • 1.02 Peripherals
  • 1.03 Software
  • 1.04 Graphics
  • 1.1 Specifications
  • 1.2 Configuration
  • Table 1.20 ‘Processor Overview
  • Figure 1.20 ICP-PIII Overview
  • 1.3 Software
  • 1.31 Linux
  • 1.32 VentureCom
  • 1.33 Windows 2000
  • 1.34 Windows CE
  • 1.35 VxWorks
  • 1.36 OS-9 x86
  • 1.37 QNX
  • 1.38 Jbed
  • 1.4 Hardware
  • 1.41 Block Diagram
  • Figure 1.41 Block Diagram
  • 1.42 Connector Location
  • Figure 1.42 Connector Locations
  • 1.43 Connector Description
  • Table 1.43 Connector Description
  • Table 1.43 Continued
  • 1.44 Front-Panel Features
  • Table 1.44 Front Panels
  • Figure 1.44 Front-Panel Options
  • 1.45 Interface Positions
  • Figure 1.45 Interfaces
• Configuration Contents
  • 2.0 Memory Map
  • Figure 2.00 System Architecture
  • Table 2.00 UMB Reservations for ISA
  • Table 2.01 Port Addressing
  • 2.1 I/O Mapped Peripherals
  • Table 2.10 Legacy I/O Map (ISA Compatible)
  • 2.2 Memory Mapped Peripherals
  • 2.3 Interrupt Routing
  • Table 2.30 PC-AT Interrupt Definitions
  • 2.4 Inova PIII Device List
  • Table 2.40 Legacy I/O Map (ISA Compatible)
  • 2.5 Interrupt Configuration
  • Table 2.50 CompactPCI Bus Interrupts
  • 2.6 Timer / Counter
  • 2.7 Watchdog
• Interfaces Contents
  • 3.0 CompactPCI J1/J2 Connector
  • 3.01 CompactPCI Connector
  • Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector
  • 3.02 ICP-PIII Connector J1 and J2
  • Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment
  • Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard)
  • Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)
  • Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)
  • Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C)
  • Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration
  • 3.1 CompactPCI Backplane
  • Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot
  • 3.2 Interfaces
  • 3.21 J7 & J12 Fast Ethernet
  • Figure 3.21 RJ45 Pinout
  • Table 3.21 Ethernet Connector Signals
  • 3.22 J17 VGA Interface
  • Figure 3.22 High-Density D-Sub VGA Interface Pinout
  • Table 3.22 Video Output Connector Signals
  • Table 3.22b Video Resolutions
  • 3.23 J16 PanelLink Interface
  • Figure 3.23 PanelLink Interface Connector
  • Table 2.12 PanelLink Interface
  • 2.24 J16 GigaSTAR Interface
  • Figure 2.24 GigaSTAR D-Sub Interface Pinout
  • Table 2.11 GigaSTAR Interface
  • 3.25 J19 USB Interface
  • Figure 3.25 USB Interface Pinout
  • Table 3.25 USB Connector Signals
  • 3.26 J15 FireWire Interface
  • Figure 3.26 FireWire Interface Pinout
  • Table 3.26 FireWire Connector Signals
  • 3.27 J20 Infrared (iRdA) Interface
  • 3.28 J20 Reset Button
  • 3.29 J14 FLASH Interface
  • 3.30 J18 Floppy Disk Interface
  • 3.31 Connecting the PIII to the Inova IPB-FPE8
  • Figure 3.31 CPU to IPB-FPE8 Connection
  • 3.32 Connecting the PIII to the Inova ICP-HD-1
  • Figure 3.32 CPU to ICP-HD-1 Connection
  • 3.33 Connecting the PIII to the Inova IPB-FPE12
  • Figure 3.33 CPU to IPB-FPE12 Connection
  • 3.34 Connecting the PIII to the Inova IPB-FPE12
  • Figure 3.34 CPU to IPB-FPE12 Connection
  • 3.35 Connecting the PIII to the ICP-FD-1
  • Figure 3.35 CPU to Slim-Line Floppy Disk Connection
• IPB-FPE8 Contents
  • A1 IPB-FPE8 CPU Extension
  • A1.1 J11 Interface for COM1, Mouse & Keyboard
  • A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)
  • Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU
  • A1.3 Stand-Alone IPB-FPE8
  • Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8
  • A1.4 IPB-FPE8MS (Theme Variation)
  • Figure A1.4 Piggyback Interface IPB-FPE8MS
  • Table A1.4 IPB-FPE8MS Connector Description
  • A1.5 IPB-FPE8MS Description
  • Figure A1.5 Top & Bottom Views of the IPB-FPE8MS
  • Table A1.5 Standard Hard-Disk & Floppy Disk Connectors
  • A1.6 Keyboard Interface
  • Figure A1.6 Keyboard Interface Pinout
  • Table A1.6 Keyboard Connector Signals
  • A1.7 Mouse Interface
  • Figure A1.7 Mouse Interface Pinout
  • Table A1.7 Mouse Connector Signals
  • A1.8 COM1 Interfaces
  • Figure A1.8 COM1 Interface Pinout
  • Table A1.8 COM1 Connector Signals
• ICP-HD Contents
  • B1 ICP-HD CPU Extension
  • B1.1 J11, J13 Interfaces
  • B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)
  • Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU
  • B1.3 IDE Carrier Board ICP-HD-1
  • Figure B1.3 IDE Carrier Board ICP-HD1
  • Table B1.3 ICP-HD-1 Connector Description
  • B1.4 ICP-HDE8MS (Theme Variation)
  • Figure B1.4 IDE Carrier ICP-HDE8MS
  • Table B1.4 IPB-HDE8MS Connector Description
  • B1.5 ICP-HDE8MS Description
  • Figure B1.5 Top & Bottom Views of the ICP-HDE8MS
  • B1.6 Keyboard Interface
  • Figure B1.6 Keyboard Interface Pinout
  • Table B1.6 Keyboard Connector Signals
  • B1.7 Mouse Interface
  • Figure B1.7 Mouse Interface Pinout
  • Table B1.7 Mouse Connector Signals
  • B1.8 COM1 & COM 2 Interfaces
  • Figure B1.8 COM1 & COM2 Interface Pinout
  • Table B1.8 COM1 & COM2 Connector Signals
• IPM-ATA
  • B1 IPM-ATA CPU Extension
  • B1.1 J1 Interfaces
  • Figure B1.1a Dedicated IPM-ATA Backplane
  • B1.1 J1 Interfaces (Contd.)
  • Figure B1.1b The Complete Connection Picture
  • B1.2 IPM-ATA-HD
  • Figure B1.2 IPM-ATA-HD Board Layout
  • Table B1.2 IPM-ATA-HD Jumper Description
  • B1.3 IPM-ATA-CF
  • Figure B1.3 IPM-ATA-CF Board Layout
  • Table B1.3 IPM-ATA-CF Jumper Description
  • B1.4 IPM-ATA-PCMCIA
  • Figure B1.4 IPM-ATA-PCMCIA Board Layout
  • Table B1.4 IPM-ATA-PCMCIA Jumper Description
  • B1.5 Device Compatibility
  • Table B1.5 Compatibility List
• IPB-FPE12 Contents
  • C1 IPB-FPE12 CPU Extension
  • C1.1 J13 Interface for LPT1 & COM2
  • C1.2 IPB-FPE12 & Front-panel (4HP or 12HP)
  • Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU
  • C1.3 LPT1 & COM2 Piggyback
  • Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12
  • Table C1.3 IPB-FPE12 Connector Description
  • C1.4 LPT1 Interface
  • Figure C1.6 LPT1 Interface Pinout
  • Table C1.6 LPT1 Connector Signals
  • C1.5 COM2 Interface
  • Figure C1.5 COM2 Interface Pinout
  • Table C1.5 COM2 Connector Signals
• IPB-RIO Contents
  • D1 IPB-RIO CPU Extension
  • D1.1 IPB-RIO-HD-FD
  • Figure D1.1 IPB-RIO-HD-FD
  • D1.2 IPB-RIO-HD-LPT-(FLEX)
  • Figure D1.2 IPB-RIO-HD-LPT-(FLEX)
  • D1.3 IPB-RIO-C-SHORT
  • Figure D1.3 IPB-RIO-C-SHORT
  • Table D1.3 Rear I/O Type ‘C’
  • D1.4 IPB-RIO-C-80MM
  • Figure D1.4 IPB-RIO-C-80MM