IBM uPD78082 - Manual (Page 53)

30
CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Data Memory Addressing (
µ
PD78081)
General Registers
32
×
8 bits
Internal ROM
8192
×
8 bits
Unusable
Internal High-speed RAM
256
×
8 bits
Special Function
Registers (SFRs)
256 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Direct Addressing
Register Indirect
Addressing
Based Addressing
Based Indexed
Addressing
F F 2 0 H
F F 1 F H
F F 0 0 H
FEFFH
FEE0H
FEDFH
F E 2 0 H
FE1FH
F E 0 0 H
FDFFH
2 0 0 0 H
1 F F F H
FFFFH
0 0 0 0 H