Document Outline

• COVER
• PREFACE
• CHAPTER 1 OUTLINE
  • 1.1 Features
  • 1.2 Applications
  • 1.3 Ordering Information
  • 1.4 Quality Grade
  • 1.5 Pin Configuration (Top View)
  • 1.6 78K/0 Series Development
  • 1.7 Block Diagram
  • 1.8 Outline of Function
  • 1.9 Differences between the uPD78081, 78082 and 78P083, the uPD78081(A), 78082(A) and 78P083(A), and the uPD78081(A2)
• CHAPTER 2 PIN FUNCTION
  • 2.1 Pin Function List
    • 2.1.1 Normal operating mode pins
    • 2.1.2 PROM programming mode pins ( uPD78P083 only)
  • 2.2 Description of Pin Functions
    • 2.2.1 P00 to P03 (Port 0)
    • 2.2.2 P10 to P17 (Port 1)
    • 2.2.3 P30 to P37 (Port 3)
    • 2.2.4 P50 to P57 (Port 5)
    • 2.2.5 P70 to P72 (Port 7)
    • 2.2.6 P100 to P101 (Port 10)
    • 2.2.7 AVREF
    • 2.2.8 AVDD
    • 2.2.9 AVSS
    • 2.2.10 RESET#
    • 2.2.11 X1 and X2
    • 2.2.12 VDD
    • 2.2.13 VSS
    • 2.2.14 VPP ( uPD78P083 only)
    • 2.2.15 IC (Mask ROM version only)
    • 2.2.16 NC (44-pin plastic QFP versions only)
  • 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
• CHAPTER 3 CPU ARCHITECTURE
  • 3.1 Memory Spaces
    • 3.1.1 Internal program memory space
    • 3.1.2 Internal data memory space
    • 3.1.3 Special Function Register (SFR) area
    • 3.1.4 Data memory addressing
  • 3.2 Processor Registers
    • 3.2.1 Control registers
    • 3.2.2 General registers
    • 3.2.3 Special Function Register (SFR)
  • 3.3 Instruction Address Addressing
    • 3.3.1 Relative addressing
    • 3.3.2 Immediate addressing
    • 3.3.3 Table indirect addressing
    • 3.3.4 Register addressing
  • 3.4 Operand Address Addressing
    • 3.4.1 Implied addressing
    • 3.4.2 Register addressing
    • 3.4.3 Direct addressing
    • 3.4.4 Short direct addressing
    • 3.4.5 Special-Function Register (SFR) addressing
    • 3.4.6 Register indirect addressing
    • 3.4.7 Based addressing
    • 3.4.8 Based indexed addressing
    • 3.4.9 Stack addressing
• CHAPTER 4 PORT FUNCTIONS
  • 4.1 Port Functions
  • 4.2 Port Configuration
    • 4.2.1 Port 0
    • 4.2.2 Port 1
    • 4.2.3 Port 3
    • 4.2.4 Port 5
    • 4.2.5 Port 7
    • 4.2.6 Port 10
  • 4.3 Port Function Control Registers
  • 4.4 Port Function Operations
    • 4.4.1 Writing to input/output port
    • 4.4.2 Reading from input/output port
    • 4.4.3 Operations on input/output port
• CHAPTER 5 CLOCK GENERATOR
  • 5.1 Clock Generator Functions
  • 5.2 Clock Generator Configuration
  • 5.3 Clock Generator Control Register
  • 5.4 System Clock Oscillator
    • 5.4.1 Main system clock oscillator
    • 5.4.2 Scaler
  • 5.5 Clock Generator Operations
  • 5.6 Changing CPU Clock Settings
    • 5.6.1 Time required for CPU clock switchover
    • 5.6.2 CPU clock switching procedure
• CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
  • 6.1 8-Bit Timer/Event Counters 5 and 6 Functions
  • 6.2 8-Bit Timer/Event Counters 5 and 6 Configurations
  • 6.3 8-Bit Timer/Event Counters 5 and 6 Control Registers
  • 6.4 8-Bit Timer/Event Counters 5 and 6 Operations
    • 6.4.1 Interval timer operations
    • 6.4.2 External event counter operation
    • 6.4.3 Square-wave output
    • 6.4.4 PWM output operations
  • 6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6
• CHAPTER 7 WATCHDOG TIMER
  • 7.1 Watchdog Timer Functions
  • 7.2 Watchdog Timer Configuration
  • 7.3 Watchdog Timer Control Registers
  • 7.4 Watchdog Timer Operations
    • 7.4.1 Watchdog timer operation
    • 7.4.2 Interval timer operation
• CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
  • 8.1 Clock Output Control Circuit Functions
  • 8.2 Clock Output Control Circuit Configuration
  • 8.3 Clock Output Function Control Registers
• CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
  • 9.1 Buzzer Output Control Circuit Functions
  • 9.2 Buzzer Output Control Circuit Configuration
  • 9.3 Buzzer Output Function Control Registers
• CHAPTER 10 A/D CONVERTER
  • 10.1 A/D Converter Functions
  • 10.2 A/D Converter Configuration
  • 10.3 A/D Converter Control Registers
  • 10.4 A/D Converter Operations
    • 10.4.1 Basic operations of A/D converter
    • 10.4.2 Input voltage and conversion results
    • 10.4.3 A/D converter operating mode
  • 10.5 A/D Converter Cautions
• CHAPTER 11 SERIAL INTERFACE CHANNEL 2
  • 11.1 Serial Interface Channel 2 Functions
  • 11.2 Serial Interface Channel 2 Configuration
  • 11.3 Serial Interface Channel 2 Control Registers
  • 11.4 Serial Interface Channel 2 Operation
    • 11.4.1 Operation stop mode
    • 11.4.2 Asynchronous serial interface (UART) mode
    • 11.4.3 3-wire serial I/O mode
• CHAPTER 12 INTERRUPT FUNCTION
  • 12.1 Interrupt Function Types
  • 12.2 Interrupt Sources and Configuration
  • 12.3 Interrupt Function Control Registers
  • 12.4 Interrupt Servicing Operations
    • 12.4.1 Non-maskable interrupt request acknowledge operation
    • 12.4.2 Maskable interrupt request acknowledge operation
    • 12.4.3 Software interrupt request acknowledge operation
    • 12.4.4 Multiple interrupt servicing
    • 12.4.5 Interrupt request reserve
• CHAPTER 13 STANDBY FUNCTION
  • 13.1 Standby Function and Configuration
    • 13.1.1 Standby function
    • 13.1.2 Standby function control register
  • 13.2 Standby Function Operations
    • 13.2.1 HALT mode
    • 13.2.2 STOP mode
• CHAPTER 14 RESET FUNCTION
  • 14.1 Reset Function
• CHAPTER 15 uPD78P083
  • 15.1 Memory Size Switching Register
  • 15.2 PROM Programming
    • 15.2.1 Operating modes
    • 15.2.2 PROM write procedure
    • 15.2.3 PROM reading procedure
  • 15.3 Erasure Procedure ( uPD78P083DU Only)
  • 15.4 Opaque Film Masking the Window ( uPD78P083DU Only)
  • 15.5 Screening of One-Time PROM Versions
• CHAPTER 16 INSTRUCTION
  • 16.1 Legends Used in Operation List
    • 16.1.1 Operand identifiers and description methods
    • 16.1.2 Description of “operation” column
    • 16.1.3 Description of “flag operation” column
  • 16.2 Operation List
  • 16.3 Instructions Listed by Addressing Type
• APPENDIX A DEVELOPMENT TOOLS
  • A.1 Language Processing Software
  • A.2 PROM Programming Tools
    • A.2.1 Hardware
    • A.2.2 Software
  • A.3 Debugging Tools
    • A.3.1 Hardware
    • A.3.2 Software (1/3)
    • A.3.2 Software (2/3)
    • A.3.2 Software (3/3)
  • A.4 OS for IBM PC
  • A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator
• APPENDIX B EMBEDDED SOFTWARE
  • B.1 Real-time OS
  • B.2 Fuzzy Inference Development Support System
• APPENDIX C REGISTER INDEX
  • C.1 Register Index
• APPENDIX D REVISION HISTORY