IBM 170 - Manual (Page 8)

6 RS/6000 7044 Model 170 Technical Overview
Following is an example of the processor card information for a 333 MHz Model
170:
Processor Card:
Part Number.................11K0857
EC Level....................D72830
Serial Number...............L200016008
FRU Number..................00P2180
Manufacture ID..............1980
Version.....................RS6K
Product Specific.(ZC).......PS=0013D92D40,LB=0009EC96A0,
SB=0005ABC3C9,NP=01,L2=01024,
PF=711,SV=3,VR=2,ER=0000
Product Specific.(ZB).......BC=30602,SG=
Physical Location: P1-C1
PS shows the processor speed in hex-number digit (0x0013D92D40 =
333000000 Hz = 333 MHz).
Following is an example of the processor card information for a 400 MHz Model
170:
Processor Card:
Part Number.................11K0864
EC Level....................D72830
Serial Number...............L200016010
FRU Number..................00P2181
Manufacture ID..............1980
Version.....................RS6K
Product Specific.(ZC).......PS=0017D78400,LB=000BEBC200,
SB=0005F5E100,NP=01,L2=04096,
PF=7D4,SV=3,VR=2,ER=0000
Product Specific.(ZB).......BC=30602,SG=
Physical Location: P1-C1
PS shows the processor speed in hex-number digit (0x0017D78400 = 400000000
Hz = 400 MHz).
Level 1 Cache
The Model 170 uses a 64 KB data and 32 KB instruction 128-way set associative
L1 cache. The size of both data and instruction cache reduces the number of
cache misses, results in more cache hits, and maximizes performance. Both data
and instruction cache are parity protected.
Level 2 Cache
The 44P Model 170 processor card has either 1 MB (333 MHz) or 4 MB
(400 MHz) of L2 cache located on the processor card. L2 cache is used to lower
the time spent accessing memory data and increase performance. The L2 cache
extends L1 cache benefits by adding more cache to the memory pipeline.
The speed of the L2 cache is dependent upon the processor speed. The L2
cache speed for the 333 MHz processor is 167 MHz (2:1 ratio) and for the 400
MHz processor is 200 MHz (2:1 ratio).
The L2 cache uses a direct mapped cache methodology. There is a dedicated
external interface to the L2 cache not shared with the 6XX bus. This allows
concurrent access to both the L2 cache and the 6XX bus.