Intel PXA255 - Manual (Page 428)

12-28 Intel® PXA255 Processor Developer’s Manual
USB Device Controller
Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC issues NAK
handshakes to all IN tokens if this bit is set and neither buffer has been triggered by writing
64-bytes or setting UDCCSx[TSP].
When DMA loads the transmit buffers, the interrupt generated by UDCCSx[TPC] can be masked
to allow data to be transmitted without core intervention.
12.6.4.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is
set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or
SET_INTERFACE. The bit’s read value is zero.
12.6.4.4 Transmit Underrun (TUR)
The transmit underrun bit is set if the transmit FIFO experiences an underrun. When the UDC
experiences an underrun, NAK handshakes are sent to the host. UDCCSx[TUR] does not generate
an interrupt and is for status only. UDCCSx[TUR] is cleared by writing a 1 to it.
12.6.4.5 Sent STALL (SST)
The sent stall bit is set by the UDC in response to FST successfully forcing a user induced STALL
on the USB bus. This bit is not set if the UDC detects a protocol violation from the host PC when a
STALL handshake is returned automatically. In either event, the core does not intervene and the
UDC clears the STALL status when the host sends a CLEAR_FEATURE command. The endpoint
operation continues normally and does not send another STALL condition, even if the
UDCCSx[SST] bit is set. To allow the software to continue to send the STALL condition on the
USB bus, the UDCCSx[FST] bit must be set again. The core writes a 1 to the sent stall bit to clear
it.
12.6.4.6 Force STALL (FST)
The core can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens.
STALL handshakes continue to be sent until the core clears this bit by sending a Clear Feature
command. The UDCCSx[SST] bit is set when the STALL state is actually entered, but this may be
delayed if the UDC is active when the UDCCSx[FST] bit is set. The UDCCSx[FST] bit is
automatically cleared when the UDCCSx[SST] bit is set. To ensure that no data is transmitted after
the Clear Feature command is sent and the host resumes IN requests, software must clear the
transmit FIFO by setting the UDCCSx[FTF] bit.
12.6.4.7 Bit 6 Reserved
Bit 6 is reserved for future use.
12.6.4.8 Transmit Short Packet (TSP)
The software uses the transmit short packet bit to indicate that the last byte of a data transfer to the
FIFO has occurred. This indicates to the UDC that a short packet or zero-sized packet is ready to
transmit. Software must not set this bit if a 64-byte packet is to be transmitted. When the data
packet is successful transmitted, the UDC clears this bit.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.