Intel PXA255 Instruction Manuals and User Guides
We have 2 Instruction Manuals and User Guides for PXA255 Intel
Manuals
| Recognized languages: | English |
|---|---|
| Pages: | 600 |
| Size: | 5.16 MB |
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Document Outline
- Intel® PXA255 Processor
- Introduction 1
- 1.1 Intel XScale® Microarchitecture Features
- 1.2 System Integration Features
- 1.2.1 Memory Controller
- 1.2.2 Clocks and Power Controllers
- 1.2.3 Universal Serial Bus (USB) Client
- 1.2.4 DMA Controller (DMAC)
- 1.2.5 LCD Controller
- 1.2.6 AC97 Controller
- 1.2.7 Inter-IC Sound (I2S) Controller
- 1.2.8 Multimedia Card (MMC) Controller
- 1.2.9 Fast Infrared (FIR) Communication Port
- 1.2.10 Synchronous Serial Protocol Controller (SSPC)
- 1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit
- 1.2.12 GPIO
- 1.2.13 UARTs
- 1.2.14 Real-Time Clock (RTC)
- 1.2.15 OS Timers
- 1.2.16 Pulse-Width Modulator (PWM)
- 1.2.17 Interrupt Control
- 1.2.18 Network Synchronous Serial Protocol Port
- System Architecture 2
- 2.1 Overview
- 2.2 Intel XScale® Microarchitecture Implementation Options
- 2.3 I/O Ordering
- 2.4 Semaphores
- 2.5 Interrupts
- 2.6 Reset
- 2.7 Internal Registers
- 2.8 Selecting Peripherals vs. General Purpose I/O
- 2.9 Power on Reset and Boot Operation
- 2.10 Power Management
- 2.11 Pin List
- 2.12 Memory Map
- 2.13 System Architecture Register Summary
- Clocks and Power Manager 3
- 3.1 Clock Manager Introduction
- 3.2 Power Manager Introduction
- 3.3 Clock Manager
- 3.4 Resets and Power Modes
- 3.5 Power Manager Registers
- 3.5.1 Power Manager Control Register (PMCR)
- 3.5.2 Power Manager General Configuration Register (PCFR)
- 3.5.3 Power Manager Wake-Up Enable Register (PWER)
- 3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)
- 3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)
- 3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)
- 3.5.7 Power Manager Sleep Status Register (PSSR)
- 3.5.8 Power Manager Scratch Pad Register (PSPR)
- 3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)
- 3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)
- 3.5.11 Reset Controller Status Register (RCSR)
- 3.6 Clocks Manager Registers
- 3.7 Coprocessor 14: Clock and Power Management
- 3.8 External Hardware Considerations
- 3.9 Clocks and Power Manager Register Summary
- System Integration Unit 4
- 4.1 General-Purpose I/O
- 4.1.1 GPIO Operation
- 4.1.2 GPIO Alternate Functions
- 4.1.3 GPIO Register Definitions
- 4.1.3.1 GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2)
- 4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)
- 4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin Output Clear Registers (GPCR0, GPCR1, GPCR2)
- 4.1.3.4 GPIO Rising Edge Detect Enable Registers (GRER0, GRER1, GRER2) and Falling Edge Detect Enable Registers (GFER0, GFER1, GFER2)
- 4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)
- 4.1.3.6 GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U, GAFR2_L, GAFR2_U)
- 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers
- 4.2 Interrupt Controller
- 4.3 Real-Time Clock (RTC)
- 4.4 Operating System (OS) Timer
- 4.5 Pulse Width Modulator
- 4.6 System Integration Unit Register Summary
- 4.1 General-Purpose I/O
- DMA Controller 5
- 5.1 DMA Description
- 5.2 Transferring Data
- 5.3 DMAC Registers
- 5.3.1 DMA Interrupt Register (DINT)
- 5.3.2 DMA Channel Control/Status Register (DCSRx)
- 5.3.3 DMA Request to Channel Map Registers (DRCMRx)
- 5.3.4 DMA Descriptor Address Registers (DDADRx)
- 5.3.5 DMA Source Address Registers
- 5.3.6 DMA Target Address Registers (DTADRx)
- 5.3.7 DMA Command Registers (DCMDx)
- 5.4 Examples
- 5.5 DMA Controller Register Summary
- Memory Controller 6
- 6.1 Overview
- 6.2 Functional Description
- 6.3 Memory System Examples
- 6.4 Memory Accesses
- 6.5 Synchronous DRAM Memory Interface
- 6.6 Synchronous Static Memory Interface
- 6.7 Asynchronous Static Memory
- 6.8 16-Bit PC Card/Compact Flash Interface
- 6.9 Companion Chip Interface
- 6.10 Options and Settings for Boot Memory
- 6.11 Hardware, Watchdog, or Sleep Reset Operation
- 6.12 GPIO Reset Procedure
- 6.13 Memory Controller Register Summary
- LCD Controller 7
- 7.1 Overview
- 7.2 LCD Controller Operation
- 7.3 Detailed Module Descriptions
- 7.4 LCD External Palette and Frame Buffers
- 7.5 Functional Timing
- 7.6 Register Descriptions
- 7.6.1 LCD Controller Control Register 0 (LCCR0)
- 7.6.2 LCD Controller Control Register 1 (LCCR1)
- 7.6.3 LCD Controller Control Register 2 (LCCR2)
- 7.6.4 LCD Controller Control Register 3 (LCCR3)
- 7.6.5 LCD Controller DMA
- 7.6.6 LCD DMA Frame Branch Registers (FBRx)
- 7.6.7 LCD Controller Status Register (LCSR)
- 7.6.8 LCD Controller Interrupt ID Register (LIIDR)
- 7.6.9 TMED RGB Seed Register (TRGBR)
- 7.6.10 TMED Control Register (TCR)
- 7.7 LCD Controller Register Summary
- Synchronous Serial Port Controller 8
- 8.1 Overview
- 8.2 Signal Description
- 8.3 Functional Description
- 8.4 Data Formats
- 8.5 FIFO Operation and Data Transfers
- 8.6 Baud-Rate Generation
- 8.7 SSP Serial Port Registers
- 8.7.1 SSP Control Register 0 (SSCR0)
- 8.7.2 SSP Control Register 1 (SSCR1)
- 8.7.2.1 Receive FIFO Interrupt Enable (RIE)
- 8.7.2.2 Transmit FIFO Interrupt Enable (TIE)
- 8.7.2.3 Loop Back Mode (LBM)
- 8.7.2.4 Serial Clock Polarity (SPO)
- 8.7.2.5 Serial Clock Phase (SPH)
- 8.7.2.6 Microwire Transmit Data Size (MWDS)
- 8.7.2.7 Transmit FIFO Interrupt/DMA Threshold (TFT)
- 8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT)
- 8.7.3 SSP Data Register (SSDR)
- 8.7.4 SSP Status Register (SSSR)
- 8.7.4.1 Transmit FIFO Not Full Flag (TNF)
- 8.7.4.2 Receive FIFO Not Empty Flag (RNE)
- 8.7.4.3 SSP Busy Flag (BSY)
- 8.7.4.4 Transmit FIFO Service Request Flag (TFS)
- 8.7.4.5 Receive FIFO Service Request Flag (RFS)
- 8.7.4.6 Receiver Overrun Status (ROR)
- 8.7.4.7 Transmit FIFO Level (TFL)
- 8.7.4.8 Receive FIFO Level (RFL)
- 8.8 SSP Controller Register Summary
- I2C Bus Interface Unit 9
- UARTs 10
- 10.1 Feature List
- 10.2 Overview
- 10.3 Signal Descriptions
- 10.4 UART Operational Description
- 10.4.1 Reset
- 10.4.2 Internal Register Descriptions
- 10.4.2.1 Receive Buffer Register (RBR)
- 10.4.2.2 Transmit Holding Register (THR)
- 10.4.2.3 Divisor Latch Registers (DLL and DLH)
- 10.4.2.4 Interrupt Enable Register (IER)
- 10.4.2.5 Interrupt Identification Register (IIR)
- 10.4.2.6 FIFO Control Register (FCR)
- 10.4.2.7 Line Control Register (LCR)
- 10.4.2.8 Line Status Register (LSR)
- 10.4.2.9 Modem Control Register (MCR)
- 10.4.2.10 Modem Status Register (MSR)
- 10.4.2.11 Scratchpad Register (SPR)
- 10.4.3 FIFO Interrupt Mode Operation
- 10.4.4 FIFO Polled Mode Operation
- 10.4.5 DMA Requests
- 10.4.6 Slow Infrared Asynchronous Interface
- 10.5 UART Register Summary
- Fast Infrared Communication Port 11
- USB Device Controller 12
- 12.1 USB Overview
- 12.2 Device Configuration
- 12.3 USB Protocol
- 12.4 UDC Hardware Connection
- 12.5 UDC Operation
- 12.5.1 Case 1: EP0 Control Read
- 12.5.2 Case 2: EP0 Control Read with a Premature Status Stage
- 12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage
- 12.5.4 Case 4: EP0 No Data Command
- 12.5.5 Case 5: EP1 Data Transmit (BULK-IN)
- 12.5.6 Case 6: EP2 Data Receive (BULK-OUT)
- 12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)
- 12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)
- 12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN)
- 12.5.10 Case 10: RESET Interrupt
- 12.5.11 Case 11: SUSPEND Interrupt
- 12.5.12 Case 12: RESUME Interrupt
- 12.6 UDC Register Definitions
- 12.6.1 UDC Control Register (UDCCR)
- 12.6.2 UDC Control Function Register (UDCCFR)
- 12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0)
- 12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)
- 12.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12)
- 12.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13)
- 12.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14)
- 12.6.8 UDC Endpoint x Control/Status Register (UDCCS5/10/15)
- 12.6.9 UDC Interrupt Control Register 0 (UICR0)
- 12.6.10 UDC Interrupt Control Register 1 (UICR1)
- 12.6.11 UDC Status/Interrupt Register 0 (USIR0)
- 12.6.11.1 Endpoint 0 Interrupt Request (IR0)
- 12.6.11.2 Endpoint 1 Interrupt Request (IR1)
- 12.6.11.3 Endpoint 2 Interrupt Request (IR2)
- 12.6.11.4 Endpoint 3 Interrupt Request (IR3)
- 12.6.11.5 Endpoint 4 Interrupt Request (IR4)
- 12.6.11.6 Endpoint 5 Interrupt Request (IR5)
- 12.6.11.7 Endpoint 6 Interrupt Request (IR6)
- 12.6.11.8 Endpoint 7 Interrupt Request (IR7)
- 12.6.12 UDC Status/Interrupt Register 1 (USIR1)
- 12.6.12.1 Endpoint 8 Interrupt Request (IR8)
- 12.6.12.2 Endpoint 9 Interrupt Request (IR9)
- 12.6.12.3 Endpoint 10 Interrupt Request (IR10)
- 12.6.12.4 Endpoint 11 Interrupt Request (IR11)
- 12.6.12.5 Endpoint 12 Interrupt Request (IR12)
- 12.6.12.6 Endpoint 13 Interrupt Request (IR13)
- 12.6.12.7 Endpoint 14 Interrupt Request (IR14)
- 12.6.12.8 Endpoint 15 Interrupt Request (IR15)
- 12.6.13 UDC Frame Number High Register (UFNHR)
- 12.6.14 UDC Frame Number Low Register (UFNLR)
- 12.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14)
- 12.6.16 UDC Endpoint 0 Data Register (UDDR0)
- 12.6.17 UDC Endpoint x Data Register (UDDR1/6/11)
- 12.6.18 UDC Endpoint x Data Register (UDDR2/7/12)
- 12.6.19 UDC Endpoint x Data Register (UDDR3/8/13)
- 12.6.20 UDC Endpoint x Data Register (UDDR4/9/14)
- 12.6.21 UDC Endpoint x Data Register (UDDR5/10/15)
- 12.7 USB Device Controller Register Summary
- AC’97 Controller Unit 13
- 13.1 Overview
- 13.2 Feature List
- 13.3 Signal Description
- 13.4 AC-link Digital Serial Interface Protocol
- 13.4.1 AC-link Audio Output Frame (SDATA_OUT)
- 13.4.2 AC-link Audio Input Frame (SDATA_IN)
- 13.4.2.1 Slot 0: Tag Phase
- 13.4.2.2 Slot 1: Status Address Port/SLOTREQ bits
- 13.4.2.3 Slot 2: Status Data Port
- 13.4.2.4 Slot 3: PCM Record Left Channel
- 13.4.2.5 Slot 4: PCM Record Right Channel
- 13.4.2.6 Slot 5: Optional Modem Line CODEC
- 13.4.2.7 Slot 6: Optional Dedicated Microphone Record Data
- 13.4.2.8 Slots 7-11: Reserved
- 13.4.2.9 Slot 12: I/O Status
- 13.5 AC-link Low Power Mode
- 13.6 ACUNIT Operation
- 13.7 Clocks and Sampling Frequencies
- 13.8 Functional Description
- 13.8.1 FIFOs
- 13.8.2 Interrupts
- 13.8.3 Registers
- 13.8.3.1 Global Control Register (GCR)
- 13.8.3.2 Global Status Register (GSR)
- 13.8.3.3 PCM-Out Control Register (POCR)
- 13.8.3.4 PCM-In Control Register (PICR)
- 13.8.3.5 PCM-Out Status Register (POSR)
- 13.8.3.6 PCM_In Status Register (PISR)
- 13.8.3.7 CODEC Access Register (CAR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
- 13.8.3.8 PCM Data Register (PCDR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
- 13.8.3.9 Mic-In Control Register (MCCR)
- 13.8.3.10 Mic-In Status Register (MCSR)
- 13.8.3.11 Mic-In Data Register (MCDR)
- 13.8.3.12 Modem-Out Control Register (MOCR)
- 13.8.3.13 Modem-In Control Register (MICR)
- 13.8.3.14 Modem-Out Status Register (MOSR)
- 13.8.3.15 Modem-In Status Register (MISR)
- 13.8.3.16 Modem Data Register (MODR)
- 13.8.3.17 Accessing CODEC Registers
- 13.9 AC’97 Register Summary
- Inter-Integrated-Circuit Sound (I2S) Controller 14
- 14.1 Overview
- 14.2 Signal Descriptions
- 14.3 Controller Operation
- 14.4 Serial Audio Clocks and Sampling Frequencies
- 14.5 Data Formats
- 14.6 Registers
- 14.6.1 Serial Audio Controller Global Control Register (SACR0)
- 14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1)
- 14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)
- 14.6.4 Serial Audio Clock Divider Register (SADIV)
- 14.6.5 Serial Audio Interrupt Clear Register (SAICR)
- 14.6.6 Serial Audio Interrupt Mask Register (SAIMR)
- 14.6.7 Serial Audio Data Register (SADR)
- 14.7 Interrupts
- 14.8 I2S Controller Register Summary
- MultiMediaCard Controller 15
- 15.1 Overview
- 15.2 MMC Controller Functional Description
- 15.3 Card Communication Protocol
- 15.4 MultiMediaCard Controller Operation
- 15.5 MMC Controller Registers
- 15.5.1 MMC_STRPCL Register
- 15.5.2 MMC_Status Register (MMC_STAT)
- 15.5.3 MMC_CLKRT Register (MMC_CLKRT)
- 15.5.4 MMC_SPI Register (MMC_SPI)
- 15.5.5 MMC_CMDAT Register (MMC_CMDAT)
- 15.5.6 MMC_RESTO Register (MMC_RESTO)
- 15.5.7 MMC_RDTO Register (MMC_RDTO)
- 15.5.8 MMC_BLKLEN Register (MMC_BLKLEN)
- 15.5.9 MMC_NOB Register (MMC_NOB)
- 15.5.10 MMC_PRTBUF Register (MMC_PRTBUF)
- 15.5.11 MMC_I_MASK Register (MMC_I_MASK)
- 15.5.12 MMC_I_REG Register (MMC_I_REG)
- 15.5.13 MMC_CMD Register (MMC_CMD)
- 15.5.14 MMC_ARGH Register (MMC_ARGH)
- 15.5.15 MMC_ARGL Register (MMC_ARGL)
- 15.5.16 MMC_RES FIFO
- 15.5.17 MMC_RXFIFO FIFO
- 15.5.18 MMC_TXFIFO FIFO
- 15.6 MultiMediaCard Controller Register Summary
- Network SSP Serial Port 16
- 16.1 Overview
- 16.2 Features
- 16.3 Signal Description
- 16.4 Operation
- 16.5 Register Descriptions
- 16.6 Network SSP Serial Port Register Summary
- Hardware UART 17
- 17.1 Overview
- 17.2 Features
- 17.3 Signal Descriptions
- 17.4 Operation
- 17.5 Register Descriptions
- 17.5.1 Receive Buffer Register (RBR)
- 17.5.2 Transmit Holding Register (THR)
- 17.5.3 Divisor Latch Registers (DLL and DLH)
- 17.5.4 Interrupt Enable Register (IER)
- 17.5.5 Interrupt Identification Register (IIR)
- 17.5.6 FIFO Control Register (FCR)
- 17.5.7 Receive FIFO Occupancy Register (FOR)
- 17.5.8 Auto-Baud Control Register (ABR)
- 17.5.9 Auto-Baud Count Register (ACR)
- 17.5.10 Line Control Register (LCR)
- 17.5.11 Line Status Register (LSR)
- 17.5.12 Modem Control Register (MCR)
- 17.5.13 Modem Status Register (MSR)
- 17.5.14 Scratchpad Register (SCR)
- 17.5.15 Infrared Selection Register (ISR)
- 17.6 Hardware UART Register Summary
- Introduction 1
| Recognized languages: | English |
|---|---|
| Pages: | 598 |
| Size: | 4.21 MB |
Show table of contents
Read manual
Document Outline
- Intel® PXA255 Processor
- Introduction 1
- 1.1 Intel® XScale™ Microarchitecture Features
- 1.2 System Integration Features
- 1.2.1 Memory Controller
- 1.2.2 Clocks and Power Controllers
- 1.2.3 Universal Serial Bus (USB) Client
- 1.2.4 DMA Controller (DMAC)
- 1.2.5 LCD Controller
- 1.2.6 AC97 Controller
- 1.2.7 Inter-IC Sound (I2S) Controller
- 1.2.8 Multimedia Card (MMC) Controller
- 1.2.9 Fast Infrared (FIR) Communication Port
- 1.2.10 Synchronous Serial Protocol Controller (SSPC)
- 1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit
- 1.2.12 GPIO
- 1.2.13 UARTs
- 1.2.14 Real-Time Clock (RTC)
- 1.2.15 OS Timers
- 1.2.16 Pulse-Width Modulator (PWM)
- 1.2.17 Interrupt Control
- 1.2.18 Network Synchronous Serial Protocol Port
- System Architecture 2
- 2.1 Overview
- 2.2 Intel® XScale™ Microarchitecture Implementation Options
- 2.3 I/O Ordering
- 2.4 Semaphores
- 2.5 Interrupts
- 2.6 Reset
- 2.7 Internal Registers
- 2.8 Selecting Peripherals vs. General Purpose I/O
- 2.9 Power on Reset and Boot Operation
- 2.10 Power Management
- 2.11 Pin List
- 2.12 Memory Map
- 2.13 System Architecture Register Summary
- Clocks and Power Manager 3
- 3.1 Clock Manager Introduction
- 3.2 Power Manager Introduction
- 3.3 Clock Manager
- 3.4 Resets and Power Modes
- 3.5 Power Manager Registers
- 3.5.1 Power Manager Control Register (PMCR)
- 3.5.2 Power Manager General Configuration Register (PCFR)
- 3.5.3 Power Manager Wake-Up Enable Register (PWER)
- 3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)
- 3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)
- 3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)
- 3.5.7 Power Manager Sleep Status Register (PSSR)
- 3.5.8 Power Manager Scratch Pad Register (PSPR)
- 3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)
- 3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)
- 3.5.11 Reset Controller Status Register (RCSR)
- 3.6 Clocks Manager Registers
- 3.7 Coprocessor 14: Clock and Power Management
- 3.8 External Hardware Considerations
- 3.9 Clocks and Power Manager Register Summary
- System Integration Unit 4
- 4.1 General-Purpose I/O
- 4.1.1 GPIO Operation
- 4.1.2 GPIO Alternate Functions
- 4.1.3 GPIO Register Definitions
- 4.1.3.1 GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2)
- 4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)
- 4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin Output Clear Registers (G...
- 4.1.3.4 GPIO Rising Edge Detect Enable Registers (GRER0, GRER1, GRER2) and Falling Edge Detect En...
- 4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)
- 4.1.3.6 GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U, GAFR2_L, GAFR2_U)
- 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers
- 4.2 Interrupt Controller
- 4.3 Real-Time Clock (RTC)
- 4.4 Operating System (OS) Timer
- 4.5 Pulse Width Modulator
- 4.6 System Integration Unit Register Summary
- 4.1 General-Purpose I/O
- DMA Controller 5
- 5.1 DMA Description
- 5.2 Transferring Data
- 5.3 DMAC Registers
- 5.3.1 DMA Interrupt Register (DINT)
- 5.3.2 DMA Channel Control/Status Register (DCSRx)
- 5.3.3 DMA Request to Channel Map Registers (DRCMRx)
- 5.3.4 DMA Descriptor Address Registers (DDADRx)
- 5.3.5 DMA Source Address Registers
- 5.3.6 DMA Target Address Registers (DTADRx)
- 5.3.7 DMA Command Registers (DCMDx)
- 5.4 Examples
- 5.5 DMA Controller Register Summary
- Memory Controller 6
- 6.1 Overview
- 6.2 Functional Description
- 6.3 Memory System Examples
- 6.4 Memory Accesses
- 6.5 Synchronous DRAM Memory Interface
- 6.6 Synchronous Static Memory Interface
- 6.7 Asynchronous Static Memory
- 6.8 16-Bit PC Card/Compact Flash Interface
- 6.9 Companion Chip Interface
- 6.10 Options and Settings for Boot Memory
- 6.11 Hardware, Watchdog, or Sleep Reset Operation
- 6.12 GPIO Reset Procedure
- 6.13 Memory Controller Register Summary
- LCD Controller 7
- 7.1 Overview
- 7.2 LCD Controller Operation
- 7.3 Detailed Module Descriptions
- 7.4 LCD External Palette and Frame Buffers
- 7.5 Functional Timing
- 7.6 Register Descriptions
- 7.6.1 LCD Controller Control Register 0 (LCCR0)
- 7.6.2 LCD Controller Control Register 1 (LCCR1)
- 7.6.3 LCD Controller Control Register 2 (LCCR2)
- 7.6.4 LCD Controller Control Register 3 (LCCR3)
- 7.6.5 LCD Controller DMA
- 7.6.6 LCD DMA Frame Branch Registers (FBRx)
- 7.6.7 LCD Controller Status Register (LCSR)
- 7.6.8 LCD Controller Interrupt ID Register (LIIDR)
- 7.6.9 TMED RGB Seed Register (TRGBR)
- 7.6.10 TMED Control Register (TCR)
- 7.7 LCD Controller Register Summary
- Synchronous Serial Port Controller 8
- 8.1 Overview
- 8.2 Signal Description
- 8.3 Functional Description
- 8.4 Data Formats
- 8.5 FIFO Operation and Data Transfers
- 8.6 Baud-Rate Generation
- 8.7 SSP Serial Port Registers
- 8.7.1 SSP Control Register 0 (SSCR0)
- 8.7.2 SSP Control Register 1 (SSCR1)
- 8.7.2.1 Receive FIFO Interrupt Enable (RIE)
- 8.7.2.2 Transmit FIFO Interrupt Enable (TIE)
- 8.7.2.3 Loop Back Mode (LBM)
- 8.7.2.4 Serial Clock Polarity (SPO)
- 8.7.2.5 Serial Clock Phase (SPH)
- 8.7.2.6 Microwire Transmit Data Size (MWDS)
- 8.7.2.7 Transmit FIFO Interrupt/DMA Threshold (TFT)
- 8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT)
- 8.7.3 SSP Data Register (SSDR)
- 8.7.4 SSP Status Register (SSSR)
- 8.7.4.1 Transmit FIFO Not Full Flag (TNF)
- 8.7.4.2 Receive FIFO Not Empty Flag (RNE)
- 8.7.4.3 SSP Busy Flag (BSY)
- 8.7.4.4 Transmit FIFO Service Request Flag (TFS)
- 8.7.4.5 Receive FIFO Service Request Flag (RFS)
- 8.7.4.6 Receiver Overrun Status (ROR)
- 8.7.4.7 Transmit FIFO Level (TFL)
- 8.7.4.8 Receive FIFO Level (RFL)
- 8.8 SSP Controller Register Summary
- I2C Bus Interface Unit 9
- UARTs 10
- 10.1 Feature List
- 10.2 Overview
- 10.3 Signal Descriptions
- 10.4 UART Operational Description
- 10.4.1 Reset
- 10.4.2 Internal Register Descriptions
- 10.4.2.1 Receive Buffer Register (RBR)
- 10.4.2.2 Transmit Holding Register (THR)
- 10.4.2.3 Divisor Latch Registers (DLL and DLH)
- 10.4.2.4 Interrupt Enable Register (IER)
- 10.4.2.5 Interrupt Identification Register (IIR)
- 10.4.2.6 FIFO Control Register (FCR)
- 10.4.2.7 Line Control Register (LCR)
- 10.4.2.8 Line Status Register (LSR)
- 10.4.2.9 Modem Control Register (MCR)
- 10.4.2.10 Modem Status Register (MSR)
- 10.4.2.11 Scratchpad Register (SPR)
- 10.4.3 FIFO Interrupt Mode Operation
- 10.4.4 FIFO Polled Mode Operation
- 10.4.5 DMA Requests
- 10.4.6 Slow Infrared Asynchronous Interface
- 10.5 UART Register Summary
- Fast Infrared Communication Port 11
- USB Device Controller 12
- 12.1 USB Overview
- 12.2 Device Configuration
- 12.3 USB Protocol
- 12.4 UDC Hardware Connection
- 12.5 UDC Operation
- 12.5.1 Case 1: EP0 Control Read
- 12.5.2 Case 2: EP0 Control Read with a Premature Status Stage
- 12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage
- 12.5.4 Case 4: EP0 No Data Command
- 12.5.5 Case 5: EP1 Data Transmit (BULK-IN)
- 12.5.6 Case 6: EP2 Data Receive (BULK-OUT)
- 12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)
- 12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)
- 12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN)
- 12.5.10 Case 10: RESET Interrupt
- 12.5.11 Case 11: SUSPEND Interrupt
- 12.5.12 Case 12: RESUME Interrupt
- 12.6 UDC Register Definitions
- 12.6.1 UDC Control Register (UDCCR)
- 12.6.2 UDC Control Function Register (UDCCFR)
- 12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0)
- 12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)
- 12.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12)
- 12.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13)
- 12.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14)
- 12.6.8 UDC Endpoint x Control/Status Register (UDCCS5/10/15)
- 12.6.9 UDC Interrupt Control Register 0 (UICR0)
- 12.6.10 UDC Interrupt Control Register 1 (UICR1)
- 12.6.11 UDC Status/Interrupt Register 0 (USIR0)
- 12.6.11.1 Endpoint 0 Interrupt Request (IR0)
- 12.6.11.2 Endpoint 1 Interrupt Request (IR1)
- 12.6.11.3 Endpoint 2 Interrupt Request (IR2)
- 12.6.11.4 Endpoint 3 Interrupt Request (IR3)
- 12.6.11.5 Endpoint 4 Interrupt Request (IR4)
- 12.6.11.6 Endpoint 5 Interrupt Request (IR5)
- 12.6.11.7 Endpoint 6 Interrupt Request (IR6)
- 12.6.11.8 Endpoint 7 Interrupt Request (IR7)
- 12.6.12 UDC Status/Interrupt Register 1 (USIR1)
- 12.6.12.1 Endpoint 8 Interrupt Request (IR8)
- 12.6.12.2 Endpoint 9 Interrupt Request (IR9)
- 12.6.12.3 Endpoint 10 Interrupt Request (IR10)
- 12.6.12.4 Endpoint 11 Interrupt Request (IR11)
- 12.6.12.5 Endpoint 12 Interrupt Request (IR12)
- 12.6.12.6 Endpoint 13 Interrupt Request (IR13)
- 12.6.12.7 Endpoint 14 Interrupt Request (IR14)
- 12.6.12.8 Endpoint 15 Interrupt Request (IR15)
- 12.6.13 UDC Frame Number High Register (UFNHR)
- 12.6.14 UDC Frame Number Low Register (UFNLR)
- 12.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14)
- 12.6.16 UDC Endpoint 0 Data Register (UDDR0)
- 12.6.17 UDC Endpoint x Data Register (UDDR1/6/11)
- 12.6.18 UDC Endpoint x Data Register (UDDR2/7/12)
- 12.6.19 UDC Endpoint x Data Register (UDDR3/8/13)
- 12.6.20 UDC Endpoint x Data Register (UDDR4/9/14)
- 12.6.21 UDC Endpoint x Data Register (UDDR5/10/15)
- 12.7 USB Device Controller Register Summary
- AC’97 Controller Unit 13
- 13.1 Overview
- 13.2 Feature List
- 13.3 Signal Description
- 13.4 AC-link Digital Serial Interface Protocol
- 13.4.1 AC-link Audio Output Frame (SDATA_OUT)
- 13.4.2 AC-link Audio Input Frame (SDATA_IN)
- 13.4.2.1 Slot 0: Tag Phase
- 13.4.2.2 Slot 1: Status Address Port/SLOTREQ bits
- 13.4.2.3 Slot 2: Status Data Port
- 13.4.2.4 Slot 3: PCM Record Left Channel
- 13.4.2.5 Slot 4: PCM Record Right Channel
- 13.4.2.6 Slot 5: Optional Modem Line CODEC
- 13.4.2.7 Slot 6: Optional Dedicated Microphone Record Data
- 13.4.2.8 Slots 7-11: Reserved
- 13.4.2.9 Slot 12: I/O Status
- 13.5 AC-link Low Power Mode
- 13.6 ACUNIT Operation
- 13.7 Clocks and Sampling Frequencies
- 13.8 Functional Description
- 13.8.1 FIFOs
- 13.8.2 Interrupts
- 13.8.3 Registers
- 13.8.3.1 Global Control Register (GCR)
- 13.8.3.2 Global Status Register (GSR)
- 13.8.3.3 PCM-Out Control Register (POCR)
- 13.8.3.4 PCM-In Control Register (PICR)
- 13.8.3.5 PCM-Out Status Register (POSR)
- 13.8.3.6 PCM_In Status Register (PISR)
- 13.8.3.7 CODEC Access Register (CAR) This is a read/write register. Ignore reads from reserved bi...
- 13.8.3.8 PCM Data Register (PCDR) This is a read/write register. Ignore reads from reserved bits....
- 13.8.3.9 Mic-In Control Register (MCCR)
- 13.8.3.10 Mic-In Status Register (MCSR)
- 13.8.3.11 Mic-In Data Register (MCDR)
- 13.8.3.12 Modem-Out Control Register (MOCR)
- 13.8.3.13 Modem-In Control Register (MICR)
- 13.8.3.14 Modem-Out Status Register (MOSR)
- 13.8.3.15 Modem-In Status Register (MISR)
- 13.8.3.16 Modem Data Register (MODR)
- 13.8.3.17 Accessing CODEC Registers
- 13.9 AC’97 Register Summary
- Inter-Integrated-Circuit Sound (I2S) Controller 14
- 14.1 Overview
- 14.2 Signal Descriptions
- 14.3 Controller Operation
- 14.4 Serial Audio Clocks and Sampling Frequencies
- 14.5 Data Formats
- 14.6 Registers
- 14.6.1 Serial Audio Controller Global Control Register (SACR0)
- 14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1)
- 14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)
- 14.6.4 Serial Audio Clock Divider Register (SADIV)
- 14.6.5 Serial Audio Interrupt Clear Register (SAICR)
- 14.6.6 Serial Audio Interrupt Mask Register (SAIMR)
- 14.6.7 Serial Audio Data Register (SADR)
- 14.7 Interrupts
- 14.8 I2S Controller Register Summary
- MultiMediaCard Controller 15
- 15.1 Overview
- 15.2 MMC Controller Functional Description
- 15.3 Card Communication Protocol
- 15.4 MultiMediaCard Controller Operation
- 15.5 MMC Controller Registers
- 15.5.1 MMC_STRPCL Register
- 15.5.2 MMC_Status Register (MMC_STAT)
- 15.5.3 MMC_CLKRT Register (MMC_CLKRT)
- 15.5.4 MMC_SPI Register (MMC_SPI)
- 15.5.5 MMC_CMDAT Register (MMC_CMDAT)
- 15.5.6 MMC_RESTO Register (MMC_RESTO)
- 15.5.7 MMC_RDTO Register (MMC_RDTO)
- 15.5.8 MMC_BLKLEN Register (MMC_BLKLEN)
- 15.5.9 MMC_NOB Register (MMC_NOB)
- 15.5.10 MMC_PRTBUF Register (MMC_PRTBUF)
- 15.5.11 MMC_I_MASK Register (MMC_I_MASK)
- 15.5.12 MMC_I_REG Register (MMC_I_REG)
- 15.5.13 MMC_CMD Register (MMC_CMD)
- 15.5.14 MMC_ARGH Register (MMC_ARGH)
- 15.5.15 MMC_ARGL Register (MMC_ARGL)
- 15.5.16 MMC_RES FIFO
- 15.5.17 MMC_RXFIFO FIFO
- 15.5.18 MMC_TXFIFO FIFO
- 15.6 MultiMediaCard Controller Register Summary
- Network SSP Serial Port 16
- 16.1 Overview
- 16.2 Features
- 16.3 Signal Description
- 16.4 Operation
- 16.5 Register Descriptions
- 16.6 Network SSP Serial Port Register Summary
- Hardware UART 17
- 17.1 Overview
- 17.2 Features
- 17.3 Signal Descriptions
- 17.4 Operation
- 17.5 Register Descriptions
- 17.5.1 Receive Buffer Register (RBR)
- 17.5.2 Transmit Holding Register (THR)
- 17.5.3 Divisor Latch Registers (DLL and DLH)
- 17.5.4 Interrupt Enable Register (IER)
- 17.5.5 Interrupt Identification Register (IIR)
- 17.5.6 FIFO Control Register (FCR)
- 17.5.7 Receive FIFO Occupancy Register (FOR)
- 17.5.8 Auto-Baud Control Register (ABR)
- 17.5.9 Auto-Baud Count Register (ACR)
- 17.5.10 Line Control Register (LCR)
- 17.5.11 Line Status Register (LSR)
- 17.5.12 Modem Control Register (MCR)
- 17.5.13 Modem Status Register (MSR)
- 17.5.14 Scratchpad Register (SCR)
- 17.5.15 Infrared Selection Register (ISR)
- 17.6 Hardware UART Register Summary
- Introduction 1