JAI CV-A33CL - Manual (Page 7)

CV-A33CL
5.3.3. Camera Link interface
The video output is Camera Link with 10 or 8 bit video placed in a base configuration. The digital
output signals follow the Camera Link standardized multiplexed signal output interface. The
Camera Link output driver is NS type DS90CR285MTD.
The data bits from the digital video, FVAL, LVAL, DVAL and EEN are multiplexed into the twisted
pairs, which are a part of the Camera Link. Trigger signals and the serial camera control are
feed directly through its own pairs. The trigger input can also be TTL on the 12 pin connector.
(TI=0 for CL. TI=1 for 12 pin HR). The serial camera control can be switches between the 12 pin
connector or CL by the internal switch SW200 on PK8387B.
The 26 pin MDR connector pin assignment follows the Camera Link base configuration.
For a detailed description of Camera Link specifications, please refer to the Camera Link
standard specifications found on www.jai.com
1
14
13
26
X0
X1
X2
X3
Xclk
SerTFG
SerTC
CC1
CC2
CC3
CC4
Sheilds
4 x
7-1
MUX
8bit 10bit
D2 D0
D3 D1
D4 D2
D5 D3
D6 D4
D7 D5
D8 D6
D9 D7
NC D8
NC D9
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
LVAL
FVAL
DVAL
EEN
Pclk
A 0 Tx0
A 1 Tx1
A 2 Tx2
A 3 Tx3
A 4 Tx4
A 5 Tx6
A 6 Tx27
A 7 Tx5
B 0 Tx7
B 1 Tx8
B 2 Tx9
B 3 Tx12
B 4 Tx13
B 5 Tx14
B 6 Tx10
B 7 Tx11
C 0 Tx15
C 1 Tx18
C 2 Tx19
C 3 Tx20
C 4 Tx21
C 5 Tx22
C 6 TX16
C 7 Tx17
Tx24
Tx25
Tx26
Tx23
Txclk
15
2
16
3
17
4
19
6
18
5
21
8
7
20
22
9
10
23
24
11
12
25
Pair 1
Pair 2
Pair 3
Pair 5
Pair 4
Pair 7
Pair 6
Pair 8
Pair 9
Pair 10
Pair 11
Sheilds
TXD out
RXD in
Ext. trig 1 in
Ground
Signal
Connector pin
CV-A33 Camera Camera Link Cable
Camera Signals
To
Frame
Grabber
Ext. Trig 2 in
Camera Link
Pin
1
14
13
26
X0
X1
X2
X3
Xclk
SerTFG
SerTC
CC1
CC2
CC3
CC4
Sheilds
4 x
7-1
MUX
8bit 10bit
D2 D0
D3 D1
D4 D2
D5 D3
D6 D4
D7 D5
D8 D6
D9 D7
NC D8
NC D9
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
LVAL
FVAL
DVAL
EEN
Pclk
A 0 Tx0
A 1 Tx1
A 2 Tx2
A 3 Tx3
A 4 Tx4
A 5 Tx6
A 6 Tx27
A 7 Tx5
B 0 Tx7
B 1 Tx8
B 2 Tx9
B 3 Tx12
B 4 Tx13
B 5 Tx14
B 6 Tx10
B 7 Tx11
C 0 Tx15
C 1 Tx18
C 2 Tx19
C 3 Tx20
C 4 Tx21
C 5 Tx22
C 6 TX16
C 7 Tx17
Tx24
Tx25
Tx26
Tx23
Txclk
15
2
16
3
17
4
19
6
18
5
21
8
7
20
22
9
10
23
24
11
12
25
Pair 1
Pair 2
Pair 3
Pair 5
Pair 4
Pair 7
Pair 6
Pair 8
Pair 9
Pair 10
Pair 11
Sheilds
TXD out
RXD in
Ext. trig 1 in
Ground
Signal
Connector pin
CV-A33 Camera Camera Link Cable
Camera Signals
To
Frame
Grabber
Ext. Trig 2 in
Camera Link
Pin Port/Signal 8bit 10bit Pin No.
Port A0 D2 D0 Tx0
Port A1 D3 D1 Tx1
Port A2 D4 D2 Tx2
Port A3 D5 D3 Tx3
Port A4 D6 D4 Tx4
Port A5 D7 D5 Tx6
Port A6 D8 D6 Tx27
Port A7 D9 D7 Tx5
Port B0 NC D8 Tx7
Port B1 NC D9 Tx8
Port B2 NC NC Tx9
Port B3 NC NC Tx12
Port B4 NC NC Tx13
Port B5 NC NC Tx14
Port B6 NC NC Tx10
Port B7 NC NC Tx11
Port C0 NC NC Tx15
Port C1 NC NC Tx18
Port C2 NC NC Tx19
Port C3 NC NC Tx20
Port C4 NC NC Tx21
Port C5 NC NC Tx22
Port C6 NC NC Tx16
Port C7 NC NC Tx17
LVAL Tx24
FVAL Tx25
DVAL Tx26
EEN Tx23
Camera Link bit allocation
D0 = LSB. D9 = MSB
TxCLK
A7 A6 EEN C7 B7 B6 A7 A6 C6
C3 C2 DVAL FVAL C5 C4 C3 C2 LVAL
B2 B1 C1 C0 B4 B3 B2 B1 B5
A1 A0 B0 A5 A3 A2 A1 A0 A4
TxOUT3
TxOUT2
TxOUT1
TxOUT0
1 pi xel cycl e
Timing
Fig. 7. Principle diagram for Camera Link base configuration interface
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