Document Outline

• Title
• Preface
• Table of contents
• 1 Guide to the S7-300 documentation
• 2 Operating and display elements
  • 2.1 Operating and display elements: CPU 31xC
    • 2.1.1 Status and Error Indicators: CPU 31xC
  • 2.2 Operating and display elements: CPU 31x
    • 2.2.1 Operating and display elements: CPU 312, 314, 315-2 DP:
    • 2.2.2 Operating and display elements: CPU 317-2 DP
    • 2.2.3 Operating and display elements: CPU 31x-2 PN/DP
    • 2.2.4 Status and error displays of the CPU 31x
• 3 Communication
  • 3.1 Interfaces
    • 3.1.1 Multi-Point Interface (MPI)
    • 3.1.2 PROFIBUS DP
    • 3.1.3 PROFINET (PN)
    • 3.1.4 Point to Point (PtP)
  • 3.2 Communication services
    • 3.2.1 Overview of communication services
    • 3.2.2 PG communication
    • 3.2.3 OP communication
    • 3.2.4 Data exchanged by means of S7 basic communication
    • 3.2.5 S7 communication
    • 3.2.6 Global data communication (MPI only)
    • 3.2.7 Routing
    • 3.2.8 PtP communication
    • 3.2.9 Data consistency
    • 3.2.10 Communication via PROFINET (only CPU 31x-2 PN/DP)
      • 3.2.10.1 PROFINET IO System
      • 3.2.10.2 Blocks in PROFINET IO
      • 3.2.10.3 System status lists (SSLs) in PROFINET IO
      • 3.2.10.4 Open communication via Industrial Ethernet
      • 3.2.10.5 SNMP communication service
  • 3.3 S7 connections
    • 3.3.1 S7 connection as communication path
    • 3.3.2 Assignment of S7 connections
    • 3.3.3 Distribution and availability of S7 connection resources
    • 3.3.4 Connection resources for routing
  • 3.4 DPV1
• 4 Memory concept
  • 4.1 Memory areas and retentivity
    • 4.1.1 CPU memory areas
    • 4.1.2 Retentivity of the load memory, system memory and RAM
    • 4.1.3 Retentivity of memory objects
    • 4.1.4 Address areas of system memory
    • 4.1.5 Properties of the Micro Memory Card (MMC)
  • 4.2 Memory functions
    • 4.2.1 General: Memory functions
    • 4.2.2 Loading user program from Micro Memory Card (MMC) to the CPU
    • 4.2.3 Handling with modules
      • 4.2.3.1 Download of new blocks or delta downloads
      • 4.2.3.2 Uploading blocks
      • 4.2.3.3 Deleting blocks
      • 4.2.3.4 Compressing blocks
      • 4.2.3.5 Promming (RAM to ROM)
    • 4.2.4 CPU memory reset and restart
    • 4.2.5 Recipes
    • 4.2.6 Measured value log files
    • 4.2.7 Backup of project data to a Micro Memory Card (MMC)
• 5 Cycle and reaction times
  • 5.1 Overview
  • 5.2 Cycle time
    • 5.2.1 Overview
    • 5.2.2 Calculating the cycle time
    • 5.2.3 Different cycle times
    • 5.2.4 Communication load
    • 5.2.5 Cycle time extension as a result of testing and commissioning functions
    • 5.2.6 Cycle extension through component-based automation (CBA)
  • 5.3 Response time
    • 5.3.1 Overview
    • 5.3.2 Shortest response time
    • 5.3.3 Longest response time
    • 5.3.4 Reducing the response time with direct I/O access
  • 5.4 Calculating method for calculating the cycle/response time
  • 5.5 Interrupt response time
    • 5.5.1 Overview
    • 5.5.2 Reproducibility of delay interrupts and watchdog interrupts
  • 5.6 Sample calculations
    • 5.6.1 Example of cycle time calculation
    • 5.6.2 Sample of response time calculation
    • 5.6.3 Example of interrupt response time calculation
• 6 Technical data of CPU 31xC
  • 6.1 General technical data
    • 6.1.1 Dimensions of CPU 31xC
    • 6.1.2 Technical data of the Micro Memory Card (MMC)
  • 6.2 CPU 312C
  • 6.3 CPU 313C
  • 6.4 CPU 313C-2 PtP and CPU 313C-2 DP
  • 6.5 CPU 314C-2 PtP and CPU 314C-2 DP
  • 6.6 Technical data of the integrated I/O
    • 6.6.1 Arrangement and usage of integrated I/Os
    • 6.6.2 Analog I/O
    • 6.6.3 Configuration
    • 6.6.4 Interrupts
    • 6.6.5 Diagnostics
    • 6.6.6 Digital inputs
    • 6.6.7 Digital outputs
    • 6.6.8 Analog inputs
    • 6.6.9 Analog outputs
• 7 Technical data of CPU 31x
  • 7.1 General technical data
    • 7.1.1 Dimensions of CPU 31x
    • 7.1.2 Technical data of the Micro Memory Card (MMC)
  • 7.2 CPU 312
  • 7.3 CPU 314
  • 7.4 CPU 315-2 DP
  • 7.5 CPU 315-2 PN/DP
  • 7.6 CPU 317-2 DP
  • 7.7 CPU 317-2 PN/DP
• Appendix
  • A.1 Information about upgrading to a CPU 31xC or CPU 31x
    • A.1.1 Area of applicability
    • A.1.2 Changed behavior of certain SFCs
    • A.1.3 Interrupt events from distributed I/Os while the CPU status is in STOP
    • A.1.4 Runtimes that change while the program is running
    • A.1.5 Converting the diagnostic addresses of DP slaves
    • A.1.6 Reusing existing hardware configurations
    • A.1.7 Replacing a CPU 31xC/31x
    • A.1.8 Using consistent data areas in the process image of a DP slave system
    • A.1.9 Load memory concept for the CPU 31xC/31x
    • A.1.10 PG/OP functions
    • A.1.11 Routing for the CPU 31xC/31x as an intelligent slave
    • A.1.12 Changed retentive behavior for CPUs with firmware >= V2.1.0
    • A.1.13 FMs/CPs with separate MPI address in the central rack of a CPU 315-2 PN/DP / CPU 317
    • A.1.14 Using loadable blocks for S7 communication for the integrated PROFINET interface
• Glossary
• Index
  • A
  • B
  • C
  • D
  • E
  • G
  • I
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • T
  • U
  • W