Document Outline

• Chapter 1 Introduction
  • 1.1 General Terms and Conventions
  • 1.2 General Description
    • Figure 1.1 LAN8710/LAN8710i System Block Diagram
  • 1.3 Architectural Overview
    • 1.3.1 Configuration
      • Figure 1.2 LAN8710/LAN8710i Architectural Overview
• Chapter 2 Pin Configuration
  • 2.1 Package Pin-out Diagram and Signal Table
    • Figure 2.1 LAN8710/LAN8710i 32-QFN Pin Assignments (TOP VIEW)
    • Table 2.1 LAN8710/LAN8710i 32-PIN QFN Pinout
• Chapter 3 Pin Description
  • Table 3.1 Buffer Types
  • 3.1 MAC Interface Signals
    • Table 3.2 MII/RMII Signals 32-QFN
  • 3.2 LED Signals
    • Table 3.3 LED Signals 32-QFN
  • 3.3 Management Signals
    • Table 3.4 Management Signals 32-QFN
  • 3.4 General Signals
    • Table 3.5 General Signals 32-QFN
  • 3.5 10/100 Line Interface Signals
    • Table 3.6 10/100 Line Interface Signals 32-QFN
  • 3.6 Analog Reference
    • Table 3.7 Analog References 32-QFN
  • 3.7 Power Signals
    • Table 3.8 Power Signals 32-QFN
• Chapter 4 Architecture Details
  • 4.1 Top Level Functional Architecture
    • Figure 4.1 100Base-TX Data Path
  • 4.2 100Base-TX Transmit
    • 4.2.1 100M Transmit Data Across the MII/RMII Interface
    • 4.2.2 4B/5B Encoding
      • Table 4.1 4B/5B Code Table
    • 4.2.3 Scrambling
    • 4.2.4 NRZI and MLT3 Encoding
    • 4.2.5 100M Transmit Driver
    • 4.2.6 100M Phase Lock Loop (PLL)
      • Figure 4.2 Receive Data Path
  • 4.3 100Base-TX Receive
    • 4.3.1 100M Receive Input
    • 4.3.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery
    • 4.3.3 NRZI and MLT-3 Decoding
    • 4.3.4 Descrambling
    • 4.3.5 Alignment
    • 4.3.6 5B/4B Decoding
    • 4.3.7 Receive Data Valid Signal
      • Figure 4.3 Relationship Between Received Data and Specific MII Signals
    • 4.3.8 Receiver Errors
    • 4.3.9 100M Receive Data Across the MII/RMII Interface
  • 4.4 10Base-T Transmit
    • 4.4.1 10M Transmit Data Across the MII/RMII Interface
    • 4.4.2 Manchester Encoding
    • 4.4.3 10M Transmit Drivers
  • 4.5 10Base-T Receive
    • 4.5.1 10M Receive Input and Squelch
    • 4.5.2 Manchester Decoding
    • 4.5.3 10M Receive Data Across the MII/RMII Interface
    • 4.5.4 Jabber Detection
  • 4.6 MAC Interface
    • 4.6.1 MII
    • 4.6.2 RMII
    • 4.6.3 MII vs. RMII Configuration
      • Table 4.2 MII/RMII Signal Mapping
  • 4.7 Auto-negotiation
    • 4.7.1 Parallel Detection
    • 4.7.2 Re-starting Auto-negotiation
    • 4.7.3 Disabling Auto-negotiation
    • 4.7.4 Half vs. Full Duplex
  • 4.8 HP Auto-MDIX Support
    • Figure 4.4 Direct Cable Connection vs. Cross-over Cable Connection
  • 4.9 Internal +1.2V Regulator Disable
    • 4.9.1 Disable the Internal +1.2V Regulator
    • 4.9.2 Enable the Internal +1.2V Regulator
  • 4.10 nINTSEL Strapping and LED Polarity Selection
    • Table 4.3 Configuration
    • Figure 4.5 nINTSEL Strapping on LED2
  • 4.11 REGOFF and LED Polarity Selection
    • Figure 4.6 REGOFF Configuration on LED1
  • 4.12 PHY Address Strapping
  • 4.13 Variable Voltage I/O
  • 4.14 Transceiver Management Control
    • 4.14.1 Serial Management Interface (SMI)
      • Figure 4.7 MDIO Timing and Frame Structure - READ Cycle
      • Figure 4.8 MDIO Timing and Frame Structure - WRITE Cycle
• Chapter 5 SMI Register Mapping
  • Table 5.1 Control Register: Register 0 (Basic)
  • Table 5.2 Status Register: Register 1 (Basic)
  • Table 5.3 PHY ID 1 Register: Register 2 (Extended)
  • Table 5.4 PHY ID 2 Register: Register 3 (Extended)
  • Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)
  • Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended)
  • Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended)
  • Table 5.8 Register 15 (Extended)
  • Table 5.9 Silicon Revision Register 16: Vendor-Specific
  • Table 5.10 Mode Control/ Status Register 17: Vendor-Specific
  • Table 5.11 Special Modes Register 18: Vendor-Specific
  • Table 5.12 Register 24: Vendor-Specific
  • Table 5.13 Register 25: Vendor-Specific
  • Table 5.14 Symbol Error Counter Register 26: Vendor-Specific
  • Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific
  • Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific
  • Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific
  • Table 5.18 Interrupt Mask Register 30: Vendor-Specific
  • Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific
  • Table 5.20 SMI Register Mapping
  • 5.1 SMI Register Format
    • Table 5.21 Register 0 - Basic Control
    • Table 5.22 Register 1 - Basic Status
    • Table 5.23 Register 2 - PHY Identifier 1
    • Table 5.24 Register 3 - PHY Identifier 2
    • Table 5.25 Register 4 - Auto Negotiation Advertisement
    • Table 5.26 Register 5 - Auto Negotiation Link Partner Ability
    • Table 5.27 Register 6 - Auto Negotiation Expansion
    • Table 5.28 Register 16 - Silicon Revision
    • Table 5.29 Register 17 - Mode Control/Status
    • Table 5.30 Register 18 - Special Modes
    • Table 5.31 Register 26 - Symbol Error Counter
    • Table 5.32 Register 27 - Special Control/Status Indications
    • Table 5.33 Register 28 - Special Internal Testability Controls
    • Table 5.34 Register 29 - Interrupt Source Flags
    • Table 5.35 Register 30 - Interrupt Mask
    • Table 5.36 Register 31 - PHY Special Control/Status
  • 5.2 Interrupt Management
    • 5.2.1 Primary Interrupt System
      • Table 5.37 Interrupt Management Table
    • 5.2.2 Alternate Interrupt System
      • Table 5.38 Alternative Interrupt System Management Table
  • 5.3 Miscellaneous Functions
    • 5.3.1 Carrier Sense
    • 5.3.2 Collision Detect
    • 5.3.3 Isolate Mode
    • 5.3.4 Link Integrity Test
    • 5.3.5 Power-Down modes
    • 5.3.6 Reset
    • 5.3.7 LED Description
    • 5.3.8 Loopback Operation
      • Figure 5.1 Near-end Loopback Block Diagram
      • Figure 5.2 Far Loopback Block Diagram
      • Figure 5.3 Connector Loopback Block Diagram
    • 5.3.9 Configuration Signals
      • Table 5.39 Pin Names for Address Bits
      • Table 5.40 MODE[2:0] Bus
      • Table 5.41 Pin Names for Mode Bits
• Chapter 6 AC Electrical Characteristics
  • 6.1 Serial Management Interface (SMI) Timing
    • Figure 6.1 SMI Timing Diagram
    • Table 6.1 SMI Timing Values
  • 6.2 MII 10/100Base-TX/RX Timings
    • 6.2.1 MII 100Base-T TX/RX Timings
      • Figure 6.2 100M MII Receive Timing Diagram
      • Table 6.2 100M MII Receive Timing Values
      • Figure 6.3 100M MII Transmit Timing Diagram
      • Table 6.3 100M MII Transmit Timing Values
    • 6.2.2 MII 10Base-T TX/RX Timings
      • Figure 6.4 10M MII Receive Timing Diagram
      • Table 6.4 10M MII Receive Timing Values
      • Figure 6.5 10M MII Transmit Timing Diagrams
      • Table 6.5 10M MII Transmit Timing Values
  • 6.3 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN)
    • 6.3.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK IN)
      • Figure 6.6 100M RMII Receive Timing Diagram (50MHz REF_CLK IN)
      • Table 6.6 100M RMII Receive Timing Values (50MHz REF_CLK IN)
      • Figure 6.7 100M RMII Transmit Timing Diagram (50MHz REF_CLK IN)
      • Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK IN)
    • 6.3.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK IN)
      • Figure 6.8 10M RMII Receive Timing Diagram (50MHz REF_CLK IN)
      • Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK IN)
      • Figure 6.9 10M RMII Transmit Timing Diagram (50MHz REF_CLK IN)
      • Table 6.9 10M RMII Transmit Timing Values (50MHz REF_CLK IN)
  • 6.4 RMII CLKIN Requirements
    • Table 6.10 RMII CLKIN (REF_CLK) Timing Values
  • 6.5 Reset Timing
    • Figure 6.10 Reset Timing Diagram
    • Table 6.11 Reset Timing Values
  • 6.6 Clock Circuit
    • Table 6.12 LAN8710/LAN8710i Crystal Specifications
• Chapter 7 DC Electrical Characteristics
  • 7.1 DC Characteristics
    • 7.1.1 Maximum Guaranteed Ratings
      • Table 7.1 Maximum Conditions
      • Table 7.2 ESD and LATCH-UP Performance
    • 7.1.2 Operating Conditions
      • Table 7.3 Recommended Operating Conditions
    • 7.1.3 Power Consumption
      • Table 7.4 Power Consumption Device Only
    • 7.1.4 DC Characteristics - Input and Output Buffers
      • Table 7.5 MII Bus Interface Signals
      • Table 7.6 LAN Interface Signals
      • Table 7.7 LED Signals
      • Table 7.8 Configuration Inputs
      • Table 7.9 General Signals
      • Table 7.10 Internal Pull-Up / Pull-Down Configurations
      • Table 7.11 100Base-TX Transceiver Characteristics
      • Table 7.12 10BASE-T Transceiver Characteristics
• Chapter 8 Application Notes
  • 8.1 Application Diagram
    • 8.1.1 MII Diagram
      • Figure 8.1 Simplified Application Diagram
    • 8.1.2 Power Supply Diagram
      • Figure 8.2 High-Level System Diagram for Power
      • Figure 8.3 High-Level System Diagram for Power
    • 8.1.3 Twisted-Pair Interface Diagram
      • Figure 8.4 Copper Interface Diagram
      • Figure 8.5 Copper Interface Diagram
  • 8.2 Magnetics Selection
• Chapter 9 Package Outline
  • Figure 9.1 LAN8710/LAN8710i-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free)
  • Table 9.1 32 Terminal QFN Package Parameters
  • Figure 9.1 QFN, 5x5 Taping Dimensions and Part Orientation
  • Figure 9.2 Reel Dimensions for 12mm Carrier Tape
  • Figure 9.3 Tape Length and Part Quantity