Document Outline

• Table of Contents
• List of Figures
• List of Tables
• Chapter 1 Preface
  • 1.1 General Terms
  • 1.2 Buffer Types
    • Table 1.1 Buffer Types
  • 1.3 Register Nomenclature
    • Table 1.2 Register Bit Types
• Chapter 2 Introduction
  • 2.1 General Description
  • 2.2 Block Diagram
    • Figure 2.1 Internal LAN9311/LAN9311i Block Diagram
    • 2.2.1 System Clocks/Reset/PME Controller
    • 2.2.2 System Interrupt Controller
    • 2.2.3 Switch Fabric
    • 2.2.4 Ethernet PHYs
    • 2.2.5 Host Bus Interface (HBI)
    • 2.2.6 Host MAC
    • 2.2.7 EEPROM Controller/Loader
    • 2.2.8 1588 Time Stamp
    • 2.2.9 GPIO/LED Controller
  • 2.3 System Configuration
    • Figure 2.2 System Block Diagram
• Chapter 3 Pin Description and Configuration
  • 3.1 Pin Diagrams
    • 3.1.1 128-VTQFP Pin Diagram
      • Figure 3.1 LAN9311 128-VTQFP Pin Assignments (TOP VIEW)
    • 3.1.2 128-XVTQFP Pin Diagram
      • Figure 3.2 LAN9311/LAN9311i 128-XVTQFP Pin Assignments (TOP VIEW)
  • 3.2 Pin Descriptions
    • Table 3.1 LAN Port 1 Pins
    • Table 3.2 LAN Port 2 Pins
    • Table 3.3 LAN Port 1 & 2 Power and Common Pins
    • Table 3.4 Host Bus Interface Pins
    • Table 3.5 EEPROM Pins
    • Table 3.6 Dedicated Configuration Strap Pins
    • Table 3.7 Miscellaneous Pins
    • Table 3.8 PLL Pins
    • Table 3.9 Core and I/O Power and Ground Pins
    • Table 3.10 No-Connect Pins
• Chapter 4 Clocking, Resets, and Power Management
  • 4.1 Clocks
  • 4.2 Resets
    • Table 4.1 Reset Sources and Affected LAN9311/LAN9311i Circuitry
    • 4.2.1 Chip-Level Resets
      • 4.2.1.1 Power-On Reset (POR)
      • 4.2.1.2 nRST Pin Reset
    • 4.2.2 Multi-Module Resets
      • 4.2.2.1 Digital Reset (DIGITAL_RST)
      • 4.2.2.2 Soft Reset (SRST)
    • 4.2.3 Single-Module Resets
      • 4.2.3.1 Port 2 PHY Reset
      • 4.2.3.2 Port 1 PHY Reset
      • 4.2.3.3 Virtual PHY Reset
    • 4.2.4 Configuration Straps
      • 4.2.4.1 Soft-Straps
        • Table 4.2 Soft-Strap Configuration Strap Definitions
      • 4.2.4.2 Hard-Straps
        • Table 4.3 Hard-Strap Configuration Strap Definitions
  • 4.3 Power Management
    • Figure 4.1 PME and PME_INT Signal Generation
    • 4.3.1 Port 1 & 2 PHY Power Management
    • 4.3.2 Host MAC Power Management
• Chapter 5 System Interrupts
  • 5.1 Functional Overview
  • 5.2 Interrupt Sources
    • Figure 5.1 Functional Interrupt Register Hierarchy
    • 5.2.1 1588 Time Stamp Interrupts
    • 5.2.2 Switch Fabric Interrupts
    • 5.2.3 Ethernet PHY Interrupts
    • 5.2.4 GPIO Interrupts
    • 5.2.5 Host MAC Interrupts
    • 5.2.6 Power Management Interrupts
    • 5.2.7 General Purpose Timer Interrupt
    • 5.2.8 Software Interrupt
    • 5.2.9 Device Ready Interrupt
• Chapter 6 Switch Fabric
  • 6.1 Functional Overview
  • 6.2 Switch Fabric CSRs
    • 6.2.1 Switch Fabric CSR Writes
      • Figure 6.1 Switch Fabric CSR Write Access Flow Diagram
    • 6.2.2 Switch Fabric CSR Reads
      • Figure 6.2 Switch Fabric CSR Read Access Flow Diagram
    • 6.2.3 Flow Control Enable Logic
      • Table 6.1 Switch Fabric Flow Control Enable Logic
  • 6.3 10/100 Ethernet MACs
    • 6.3.1 Receive MAC
      • 6.3.1.1 Receive Counters
    • 6.3.2 Transmit MAC
      • 6.3.2.1 Transmit Counters
  • 6.4 Switch Engine (SWE)
    • 6.4.1 MAC Address Lookup Table
      • Figure 6.3 ALR Table Entry Structure
      • 6.4.1.1 Learning/Aging/Migration
      • 6.4.1.2 Static Entries
      • 6.4.1.3 Multicast Pruning
      • 6.4.1.4 Address Filtering
      • 6.4.1.5 Spanning Tree Port State Override
      • 6.4.1.6 MAC Destination Address Lookup Priority
      • 6.4.1.7 Host Access
    • 6.4.2 Forwarding Rules
    • 6.4.3 Transmit Priority Queue Selection
      • Figure 6.4 Switch Engine Transmit Queue Selection
      • Figure 6.5 Switch Engine Transmit Queue Calculation
      • 6.4.3.1 Port Default Priority
      • 6.4.3.2 IP Precedence Based Priority
      • 6.4.3.3 DIFFSERV Based Priority
      • 6.4.3.4 VLAN Priority
    • 6.4.4 VLAN Support
      • Figure 6.6 VLAN Table Entry Structure
    • 6.4.5 Spanning Tree Support
      • Table 6.2 Spanning Tree States
    • 6.4.6 Ingress Flow Metering and Coloring
      • Table 6.3 Typical Ingress Rate Settings
      • 6.4.6.1 Ingress Flow Calculation
        • Figure 6.7 Switch Engine Ingress Flow Priority Selection
        • Figure 6.8 Switch Engine Ingress Flow Priority Calculation
    • 6.4.7 Broadcast Storm Control
      • Table 6.4 Typical Broadcast Rate Settings
    • 6.4.8 IPv4 IGMP / IPv6 MLD Support
    • 6.4.9 Port Mirroring
    • 6.4.10 Host CPU Port Special Tagging
      • 6.4.10.1 Packets from the Host CPU
      • 6.4.10.2 Packets to the Host CPU
    • 6.4.11 Counters
  • 6.5 Buffer Manager (BM)
    • 6.5.1 Packet Buffer Allocation
      • 6.5.1.1 Buffer Limits and Flow Control Levels
    • 6.5.2 Random Early Discard (RED)
    • 6.5.3 Transmit Queues
    • 6.5.4 Transmit Priority Queue Servicing
    • 6.5.5 Egress Rate Limiting (Leaky Bucket)
      • Table 6.5 Typical Egress Rate Settings
    • 6.5.6 Adding, Removing, and Changing VLAN Tags
      • Figure 6.9 Hybrid Port Tagging and Un-tagging
    • 6.5.7 Counters
  • 6.6 Switch Fabric Interrupts
• Chapter 7 Ethernet PHYs
  • 7.1 Functional Overview
    • 7.1.1 PHY Addressing
      • Table 7.1 Default PHY Serial MII Addressing
  • 7.2 Port 1 & 2 PHYs
    • Figure 7.1 Port x PHY Block Diagram
    • 7.2.1 100BASE-TX Transmit
      • Figure 7.2 100BASE-TX Transmit Data Path
      • 7.2.1.1 MII MAC Interface
      • 7.2.1.2 4B/5B Encoder
        • Table 7.2 4B/5B Code Table
      • 7.2.1.3 Scrambler and PISO
      • 7.2.1.4 NRZI and MLT-3 Encoding
      • 7.2.1.5 100M Transmit Driver
      • 7.2.1.6 100M Phase Lock Loop (PLL)
    • 7.2.2 100BASE-TX Receive
      • Figure 7.3 100BASE-TX Receive Data Path
      • 7.2.2.1 A/D Converter
      • 7.2.2.2 DSP: Equalizer, BLW Correction and Clock/Data Recovery
      • 7.2.2.3 NRZI and MLT-3 Decoding
      • 7.2.2.4 Descrambler and SIPO
      • 7.2.2.5 5B/4B Decoding
      • 7.2.2.6 Receiver Errors
      • 7.2.2.7 MII MAC Interface
    • 7.2.3 10BASE-T Transmit
      • 7.2.3.1 MII MAC Interface
      • 7.2.3.2 10M TX Driver and PLL
    • 7.2.4 10BASE-T Receive
      • 7.2.4.1 Filter and Squelch
      • 7.2.4.2 10M RX and PLL
      • 7.2.4.3 MII MAC Interface
      • 7.2.4.4 Jabber Detection
    • 7.2.5 PHY Auto-negotiation
      • 7.2.5.1 PHY Pause Flow Control
      • 7.2.5.2 Parallel Detection
      • 7.2.5.3 Restarting Auto-Negotiation
      • 7.2.5.4 Disabling Auto-Negotiation
      • 7.2.5.5 Half Vs. Full-Duplex
    • 7.2.6 HP Auto-MDIX
      • Figure 7.4 Direct Cable Connection vs. Cross-Over Cable Connection
    • 7.2.7 MII MAC Interface
    • 7.2.8 PHY Management Control
      • 7.2.8.1 PHY Interrupts
        • Table 7.3 PHY Interrupt Sources
    • 7.2.9 PHY Power-Down Modes
      • 7.2.9.1 PHY General Power-Down
      • 7.2.9.2 PHY Energy Detect Power-Down
    • 7.2.10 PHY Resets
      • 7.2.10.1 PHY Software Reset via RESET_CTL
      • 7.2.10.2 PHY Software Reset via PHY_BASIC_CTRL_x
      • 7.2.10.3 PHY Power-Down Reset
    • 7.2.11 LEDs
    • 7.2.12 Required Ethernet Magnetics
  • 7.3 Virtual PHY
    • 7.3.1 Virtual PHY Auto-Negotiation
      • 7.3.1.1 Parallel Detection
      • 7.3.1.2 Disabling Auto-Negotiation
      • 7.3.1.3 Virtual PHY Pause Flow Control
    • 7.3.2 Virtual PHY Resets
      • 7.3.2.1 Virtual PHY Software Reset via RESET_CTL
      • 7.3.2.2 Virtual PHY Software Reset via VPHY_BASIC_CTRL
      • 7.3.2.3 Virtual PHY Software Reset via PMT_CTRL
• Chapter 8 Host Bus Interface (HBI)
  • 8.1 Functional Overview
  • 8.2 Host Memory Mapping
  • 8.3 Host Data Bus
    • 8.3.1 16-Bit Bus Writes
    • 8.3.2 16-Bit Bus Read
  • 8.4 Host Endianess
    • Figure 8.1 Little Endian Byte Ordering
    • Figure 8.2 Big Endian Byte Ordering
  • 8.5 Host Interface Timing
    • 8.5.1 Special Situations
      • 8.5.1.1 Reset Ending During a Read Cycle
      • 8.5.1.2 Reset Ending Between Halves of a 16-Bit Read Pair
      • 8.5.1.3 Writes Following a Reset
    • 8.5.2 Special Restrictions on Back-to Back Write-Read Cycles
      • Table 8.1 Read After Write Timing Rules
    • 8.5.3 Special Restrictions on Back-to-Back Read Cycles
      • Table 8.2 Read After Read Timing Rules
    • 8.5.4 PIO Reads
      • Figure 8.3 Functional Timing for PIO Read Operation
    • 8.5.5 PIO Burst Reads
      • Figure 8.4 Functional Timing for PIO Burst Read Operation
    • 8.5.6 RX Data FIFO Direct PIO Reads
      • Figure 8.5 Functional Timing for RX Data FIFO Direct PIO Read Operation
    • 8.5.7 RX Data FIFO Direct PIO Burst Reads
      • Figure 8.6 Functional Timing for RX Data FIFO Direct PIO Burst Read Operation
    • 8.5.8 PIO Writes
      • Figure 8.7 Functional Timing for PIO Write Operation
    • 8.5.9 TX Data FIFO Direct PIO Writes
      • Figure 8.8 Functional Timing for TX Data FIFO Direct PIO Write Operation
  • 8.6 HBI Interrupts
• Chapter 9 Host MAC
  • 9.1 Functional Overview
  • 9.2 Flow Control
    • 9.2.1 Full-Duplex Flow Control
    • 9.2.2 Half-Duplex Flow Control (Backpressure)
  • 9.3 Virtual Local Area Network (VLAN) Support
    • Figure 9.1 VLAN Frame
  • 9.4 Address Filtering
    • Table 9.1 Address Filtering Modes
    • 9.4.1 Perfect Filtering
    • 9.4.2 Hash Only Filtering
    • 9.4.3 Hash Perfect Filtering
    • 9.4.4 Inverse Filtering
  • 9.5 Wake-up Frame Detection
    • Table 9.2 Wake-Up Frame Filter Register Structure
    • Table 9.3 Filter i Byte Mask Bit Definitions
    • Table 9.4 Filter i Command Bit Definitions
    • Table 9.5 Filter i Offset Bit Definitions
    • Table 9.6 Filter i CRC-16 Bit Definitions
    • 9.5.1 Magic Packet Detection
  • 9.6 Host MAC Address
    • Table 9.7 EEPROM Byte Ordering and Register Correlation
    • Figure 9.2 Example EEPROM MAC Address Setup
  • 9.7 FIFOs
    • 9.7.1 TX/RX FIFOs
    • 9.7.2 MIL FIFOs
    • 9.7.3 FIFO Memory Allocation Configuration
      • Table 9.8 TX/RX FIFO Configurable Sizes
      • Table 9.9 Valid TX/RX FIFO Allocations
  • 9.8 TX Data Path Operation
    • Figure 9.3 Simplified Host TX Flow Diagram
    • 9.8.1 TX Buffer Format
      • Figure 9.4 TX Buffer Format
    • 9.8.2 TX Command Format
      • 9.8.2.1 TX Command ‘A’
        • Table 9.10 TX Command 'A' Format
      • 9.8.2.2 TX Command ‘B’
        • Table 9.11 TX Command 'B' Format
    • 9.8.3 TX Data Format
      • Table 9.12 TX DATA Start Offset
      • 9.8.3.1 TX Buffer Fragmentation Rules
      • 9.8.3.2 Calculating Worst-Case TX MIL FIFO Usage
    • 9.8.4 TX Status Format
    • 9.8.5 Calculating Actual TX Data FIFO Usage
    • 9.8.6 Transmit Examples
      • 9.8.6.1 TX Example 1
        • Figure 9.5 TX Example 1
      • 9.8.6.2 TX Example 2
        • Figure 9.6 TX Example 2
    • 9.8.7 Transmitter Errors
    • 9.8.8 Stopping and Starting the Transmitter
  • 9.9 RX Data Path Operation
    • 9.9.1 RX Slave PIO Operation
      • Figure 9.7 Host Receive Routine Using Interrupts
      • Figure 9.8 Host Receive Routine Using Polling
      • 9.9.1.1 Receive Data FIFO Fast Forward
      • 9.9.1.2 Force Receiver Discard (Receiver Dump)
    • 9.9.2 RX Packet Format
      • Figure 9.9 RX Packet Format
    • 9.9.3 RX Status Format
    • 9.9.4 Stopping and Starting the Receiver
    • 9.9.5 Receiver Errors
• Chapter 10 Serial Management
  • 10.1 Functional Overview
  • 10.2 I2C/Microwire Master EEPROM Controller
    • Table 10.1 I2C/Microwire Master Serial Management Pins Characteristics
    • 10.2.1 EEPROM Controller Operation
      • Figure 10.1 EEPROM Access Flow Diagram
    • 10.2.2 I2C EEPROM
      • Table 10.2 I2C EEPROM Size Ranges
      • 10.2.2.1 I2C Protocol Overview
        • Figure 10.2 I2C Cycle
      • 10.2.2.2 I2C EEPROM Device Addressing
        • Figure 10.3 I2C EEPROM Addressing
      • 10.2.2.3 I2C EEPROM Byte Read
        • Figure 10.4 I2C EEPROM Byte Read
      • 10.2.2.4 I2C EEPROM Sequential Byte Reads
        • Figure 10.5 I2C EEPROM Sequential Byte Reads
      • 10.2.2.5 I2C EEPROM Byte Writes
        • Figure 10.6 I2C EEPROM Byte Write
    • 10.2.3 Microwire EEPROM
      • Table 10.3 Microwire EEPROM Size Ranges
      • 10.2.3.1 Microwire Master Commands
        • Table 10.4 Microwire Command Set for 7 Address Bits
        • Table 10.5 Microwire Command Set for 9 Address Bits
        • Table 10.6 Microwire Command Set for 11 Address Bits
      • 10.2.3.2 ERASE (Erase Location)
        • Figure 10.7 EEPROM ERASE Cycle
      • 10.2.3.3 ERAL (Erase All)
        • Figure 10.8 EEPROM ERAL Cycle
      • 10.2.3.4 EWDS (Erase/Write Disable)
        • Figure 10.9 EEPROM EWDS Cycle
      • 10.2.3.5 EWEN (Erase/Write Enable)
        • Figure 10.10 EEPROM EWEN Cycle
      • 10.2.3.6 READ (Read Location)
        • Figure 10.11 EEPROM READ Cycle
      • 10.2.3.7 WRITE (Write Location)
        • Figure 10.12 EEPROM WRITE Cycle
      • 10.2.3.8 WRAL (Write All)
        • Figure 10.13 EEPROM WRAL Cycle
    • 10.2.4 EEPROM Loader
      • Table 10.7 EEPROM Contents Format Overview
      • 10.2.4.1 EEPROM Loader Operation
        • Figure 10.14 EEPROM Loader Flow Diagram
      • 10.2.4.2 EEPROM Valid Flag
      • 10.2.4.3 MAC Address
        • 10.2.4.3.1 Host MAC Address Reload
      • 10.2.4.4 Soft-Straps
        • Table 10.8 EEPROM Configuration Bits
        • 10.2.4.4.1 PHY Registers Synchronization
        • 10.2.4.4.2 Virtual PHY Registers Synchronization
        • 10.2.4.4.3 LED and Manual Flow Control Register Synchronization
      • 10.2.4.5 Register Data
      • 10.2.4.6 EEPROM Loader Finished Wait-State
      • 10.2.4.7 Reset Sequence and EEPROM Loader
• Chapter 11 IEEE 1588 Hardware Time Stamp Unit
  • 11.1 Functional Overview
    • 11.1.1 IEEE 1588
    • 11.1.2 Block Diagram
      • Figure 11.1 IEEE 1588 Block Diagram
  • 11.2 IEEE 1588 Time Stamp
    • Table 11.1 IEEE 1588 Message Type Detection
    • Figure 11.2 IEEE 1588 Message Time Stamp Point
    • Table 11.2 Time Stamp Capture Delay
    • 11.2.1 Capture Locking
    • 11.2.2 PTP Message Detection
      • Table 11.3 PTP Multicast Addresses
  • 11.3 IEEE 1588 Clock
    • Table 11.4 Typical IEEE 1588 Clock Addend Values
  • 11.4 IEEE 1588 Clock/Events
  • 11.5 IEEE 1588 GPIOs
  • 11.6 IEEE 1588 Interrupts
• Chapter 12 General Purpose Timer & Free-Running Clock
  • 12.1 General Purpose Timer
  • 12.2 Free-Running Clock
• Chapter 13 GPIO/LED Controller
  • 13.1 Functional Overview
  • 13.2 GPIO Operation
    • 13.2.1 GPIO IEEE 1588 Timestamping
      • 13.2.1.1 IEEE 1588 GPIO Inputs
      • 13.2.1.2 IEEE 1588 GPIO Outputs
    • 13.2.2 GPIO Interrupts
      • 13.2.2.1 GPIO Interrupt Polarity
      • 13.2.2.2 IEEE 1588 GPIO Interrupts
  • 13.3 LED Operation
    • Table 13.1 LED Operation as a Function of LED_CFG[9:8]
• Chapter 14 Register Descriptions
  • Figure 14.1 LAN9311/LAN9311i Base Register Memory Map
  • 14.1 TX/RX FIFO Ports
    • 14.1.1 TX/RX Data FIFO’s
    • 14.1.2 TX/RX Status FIFO’s
    • 14.1.3 Direct FIFO Access Mode
  • 14.2 System Control and Status Registers
    • Table 14.1 System Control and Status Registers
    • 14.2.1 Interrupts
      • 14.2.1.1 Interrupt Configuration Register (IRQ_CFG)
      • 14.2.1.2 Interrupt Status Register (INT_STS)
      • 14.2.1.3 Interrupt Enable Register (INT_EN)
      • 14.2.1.4 FIFO Level Interrupt Register (FIFO_INT)
    • 14.2.2 Host MAC & FIFO’s
      • 14.2.2.1 Receive Configuration Register (RX_CFG)
      • 14.2.2.2 Transmit Configuration Register (TX_CFG)
      • 14.2.2.3 Receive Datapath Control Register (RX_DP_CTRL)
      • 14.2.2.4 RX FIFO Information Register (RX_FIFO_INF)
      • 14.2.2.5 TX FIFO Information Register (TX_FIFO_INF)
      • 14.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP)
      • 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD)
      • 14.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA)
      • 14.2.2.9 Host MAC Automatic Flow Control Configuration Register (AFC_CFG)
        • Table 14.2 Backpressure Duration Bit Mapping
    • 14.2.3 GPIO/LED
      • 14.2.3.1 General Purpose I/O Configuration Register (GPIO_CFG)
      • 14.2.3.2 General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)
      • 14.2.3.3 General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
      • 14.2.3.4 LED Configuration Register (LED_CFG)
    • 14.2.4 EEPROM
      • 14.2.4.1 EEPROM Command Register (E2P_CMD)
      • 14.2.4.2 EEPROM Data Register (E2P_DATA)
    • 14.2.5 IEEE 1588
      • 14.2.5.1 Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x)
      • 14.2.5.2 Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x)
      • 14.2.5.3 Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)
      • 14.2.5.4 Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)
      • 14.2.5.5 Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x)
      • 14.2.5.6 Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x)
      • 14.2.5.7 Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x)
      • 14.2.5.8 Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x)
      • 14.2.5.9 GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8)
      • 14.2.5.10 GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8)
      • 14.2.5.11 GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9)
      • 14.2.5.12 GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9)
      • 14.2.5.13 1588 Clock High-DWORD Register (1588_CLOCK_HI)
      • 14.2.5.14 1588 Clock Low-DWORD Register (1588_CLOCK_LO)
      • 14.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDEND)
      • 14.2.5.16 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)
      • 14.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO)
      • 14.2.5.18 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)
      • 14.2.5.19 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO)
      • 14.2.5.20 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI)
      • 14.2.5.21 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO)
      • 14.2.5.22 1588 Configuration Register (1588_CONFIG)
      • 14.2.5.23 1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
      • 14.2.5.24 1588 Command Register (1588_CMD)
    • 14.2.6 Switch Fabric
      • 14.2.6.1 Port 1 Manual Flow Control Register (MANUAL_FC_1)
      • 14.2.6.2 Port 2 Manual Flow Control Register (MANUAL_FC_2)
      • 14.2.6.3 Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII)
      • 14.2.6.4 Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA)
      • 14.2.6.5 Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
      • 14.2.6.6 Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH)
      • 14.2.6.7 Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)
      • 14.2.6.8 Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
        • Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map
    • 14.2.7 PHY Management Interface (PMI)
      • 14.2.7.1 PHY Management Interface Data Register (PMI_DATA)
      • 14.2.7.2 PHY Management Interface Access Register (PMI_ACCESS)
    • 14.2.8 Virtual PHY
      • Table 14.4 Virtual PHY MII Serially Adressable Register Index
      • 14.2.8.1 Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
      • 14.2.8.2 Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)
      • 14.2.8.3 Virtual PHY Identification MSB Register (VPHY_ID_MSB)
      • 14.2.8.4 Virtual PHY Identification LSB Register (VPHY_ID_LSB)
      • 14.2.8.5 Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)
      • 14.2.8.6 Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY)
        • Table 14.5 Emulated Link Partner Pause Flow Control Ability Default Values
      • 14.2.8.7 Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP)
      • 14.2.8.8 Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
    • 14.2.9 Miscellaneous
      • 14.2.9.1 Chip ID and Revision (ID_REV)
      • 14.2.9.2 Byte Order Test Register (BYTE_TEST)
      • 14.2.9.3 Hardware Configuration Register (HW_CFG)
      • 14.2.9.4 Power Management Control Register (PMT_CTRL)
      • 14.2.9.5 General Purpose Timer Configuration Register (GPT_CFG)
      • 14.2.9.6 General Purpose Timer Count Register (GPT_CNT)
      • 14.2.9.7 Free Running 25MHz Counter Register (FREE_RUN)
      • 14.2.9.8 Reset Control Register (RESET_CTL)
  • 14.3 Host MAC Control and Status Registers
    • Table 14.6 Host MAC Adressable Registers
    • 14.3.1 Host MAC Control Register (HMAC_CR)
    • 14.3.2 Host MAC Address High Register (HMAC_ADDRH)
    • 14.3.3 Host MAC Address Low Register (HMAC_ADDRL)
    • 14.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH)
    • 14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL)
    • 14.3.6 Host MAC MII Access Register (HMAC_MII_ACC)
    • 14.3.7 Host MAC MII Data Register (HMAC_MII_DATA)
    • 14.3.8 Host MAC Flow Control Register (HMAC_FLOW)
    • 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1)
    • 14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2)
    • 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF)
    • 14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR)
  • 14.4 Ethernet PHY Control and Status Registers
    • 14.4.1 Virtual PHY Registers
    • 14.4.2 Port 1 & 2 PHY Registers
      • Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers
      • 14.4.2.1 Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
      • 14.4.2.2 Port x PHY Basic Status Register (PHY_BASIC_STATUS_x)
      • 14.4.2.3 Port x PHY Identification MSB Register (PHY_ID_MSB_x)
      • 14.4.2.4 Port x PHY Identification LSB Register (PHY_ID_LSB_x)
      • 14.4.2.5 Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
        • Table 14.8 10BASE-T Full Duplex Advertisement Default Value
        • Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value
      • 14.4.2.6 Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x)
      • 14.4.2.7 Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x)
      • 14.4.2.8 Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
      • 14.4.2.9 Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
        • Table 14.10 MODE[2:0] Definitions
      • 14.4.2.10 Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
        • Table 14.11 Auto-MDIX Enable and Auto-MDIX State Bit Functionality
      • 14.4.2.11 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)
      • 14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
      • 14.4.2.13 Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x)
  • 14.5 Switch Fabric Control and Status Registers
    • Table 14.12 Indirectly Accessible Switch Control and Status Registers
    • 14.5.1 General Switch CSRs
      • 14.5.1.1 Switch Device ID Register (SW_DEV_ID)
      • 14.5.1.2 Switch Reset Register (SW_RESET)
      • 14.5.1.3 Switch Global Interrupt Mask Register (SW_IMR)
      • 14.5.1.4 Switch Global Interrupt Pending Register (SW_IPR)
    • 14.5.2 Switch Port 0, Port 1, and Port 2 CSRs
      • 14.5.2.1 Port x MAC Version ID Register (MAC_VER_ID_x)
      • 14.5.2.2 Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
      • 14.5.2.3 Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x)
      • 14.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x)
      • 14.5.2.5 Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)
      • 14.5.2.6 Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)
      • 14.5.2.7 Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)
      • 14.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)
      • 14.5.2.9 Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x)
      • 14.5.2.10 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x)
      • 14.5.2.11 Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)
      • 14.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x)
      • 14.5.2.13 Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x)
      • 14.5.2.14 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x)
      • 14.5.2.15 Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x)
      • 14.5.2.16 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)
      • 14.5.2.17 Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x)
      • 14.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x)
      • 14.5.2.19 Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x)
      • 14.5.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x)
      • 14.5.2.21 Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x)
      • 14.5.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x)
      • 14.5.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)
      • 14.5.2.24 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x)
      • 14.5.2.25 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x)
      • 14.5.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x)
      • 14.5.2.27 Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x)
      • 14.5.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x)
      • 14.5.2.29 Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x)
      • 14.5.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x)
      • 14.5.2.31 Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x)
      • 14.5.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x)
      • 14.5.2.33 Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)
      • 14.5.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x)
      • 14.5.2.35 Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x)
      • 14.5.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x)
      • 14.5.2.37 Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x)
      • 14.5.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x)
      • 14.5.2.39 Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)
      • 14.5.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x)
      • 14.5.2.41 Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x)
      • 14.5.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)
      • 14.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x)
      • 14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x)
    • 14.5.3 Switch Engine CSRs
      • 14.5.3.1 Switch Engine ALR Command Register (SWE_ALR_CMD)
      • 14.5.3.2 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0)
      • 14.5.3.3 Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1)
      • 14.5.3.4 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)
      • 14.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)
      • 14.5.3.6 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS)
      • 14.5.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG)
      • 14.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD)
      • 14.5.3.9 Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA)
      • 14.5.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA)
      • 14.5.3.11 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS)
      • 14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)
      • 14.5.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA)
      • 14.5.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA)
      • 14.5.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)
      • 14.5.3.16 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)
      • 14.5.3.17 Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG)
      • 14.5.3.18 Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN)
      • 14.5.3.19 Switch Engine Port State Register (SWE_PORT_STATE)
      • 14.5.3.20 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)
      • 14.5.3.21 Switch Engine Port Mirroring Register (SWE_PORT_MIRROR)
      • 14.5.3.22 Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP)
      • 14.5.3.23 Switch Engine Broadcast Throttling Register (SWE_BCST_THROT)
      • 14.5.3.24 Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER)
      • 14.5.3.25 Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG)
      • 14.5.3.26 Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)
        • 14.5.3.26.1 Ingress Rate Table Registers
          • Table 14.13 Metering/Color Table Register Descriptions
      • 14.5.3.27 Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS)
      • 14.5.3.28 Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA)
      • 14.5.3.29 Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA)
      • 14.5.3.30 Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII)
      • 14.5.3.31 Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1)
      • 14.5.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2)
      • 14.5.3.33 Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII)
      • 14.5.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1)
      • 14.5.3.35 Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2)
      • 14.5.3.36 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII)
      • 14.5.3.37 Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1)
      • 14.5.3.38 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2)
      • 14.5.3.39 Switch Engine Interrupt Mask Register (SWE_IMR)
      • 14.5.3.40 Switch Engine Interrupt Pending Register (SWE_IPR)
    • 14.5.4 Buffer Manager CSRs
      • 14.5.4.1 Buffer Manager Configuration Register (BM_CFG)
      • 14.5.4.2 Buffer Manager Drop Level Register (BM_DROP_LVL)
      • 14.5.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)
      • 14.5.4.4 Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL)
      • 14.5.4.5 Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL)
      • 14.5.4.6 Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII)
      • 14.5.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1)
      • 14.5.4.8 Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2)
      • 14.5.4.9 Buffer Manager Reset Status Register (BM_RST_STS)
      • 14.5.4.10 Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD)
      • 14.5.4.11 Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA)
      • 14.5.4.12 Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA)
      • 14.5.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE)
      • 14.5.4.14 Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01)
      • 14.5.4.15 Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_02_03)
      • 14.5.4.16 Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11)
      • 14.5.4.17 Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13)
      • 14.5.4.18 Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21)
      • 14.5.4.19 Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_22_23)
      • 14.5.4.20 Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII)
      • 14.5.4.21 Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1)
      • 14.5.4.22 Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2)
      • 14.5.4.23 Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII)
      • 14.5.4.24 Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1)
      • 14.5.4.25 Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)
      • 14.5.4.26 Buffer Manager Interrupt Mask Register (BM_IMR)
      • 14.5.4.27 Buffer Manager Interrupt Pending Register (BM_IPR)
• Chapter 15 Operational Characteristics
  • 15.1 Absolute Maximum Ratings*
  • 15.2 Operating Conditions**
  • 15.3 Power Consumption
    • Table 15.1 Supply and Current (10BASE-T Full-Duplex)
    • Table 15.2 Supply and Current (100BASE-TX Full-Duplex)
  • 15.4 DC Specifications
    • Table 15.3 I/O Buffer Characteristics
    • Table 15.4 100BASE-TX Transceiver Characteristics
    • Table 15.5 10BASE-T Transceiver Characteristics
  • 15.5 AC Specifications
    • 15.5.1 Equivalent Test Load
      • Figure 15.1 Output Equivalent Test Load
    • 15.5.2 Reset and Configuration Strap Timing
      • Figure 15.2 nRST Reset Pin Timing
      • Table 15.6 nRST Reset Pin Timing Values
    • 15.5.3 Power-On Configuration Strap Valid Timing
      • Figure 15.3 Power-On Configuration Strap Latching Timing
      • Table 15.7 Power-On Configuration Strap Latching Timing Values
    • 15.5.4 PIO Read Cycle Timing
      • Figure 15.4 PIO Read Cycle Timing
      • Table 15.8 PIO Read Cycle Timing Values
    • 15.5.5 PIO Burst Read Cycle Timing
      • Figure 15.5 PIO Burst Read Cycle Timing
      • Table 15.9 PIO Burst Read Cycle Timing Values
    • 15.5.6 RX Data FIFO Direct PIO Read Cycle Timing
      • Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing
      • Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values
    • 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing
      • Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing
      • Table 15.11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values
    • 15.5.8 PIO Write Cycle Timing
      • Figure 15.8 PIO Write Cycle Timing
      • Table 15.12 PIO Write Cycle Timing Values
    • 15.5.9 TX Data FIFO Direct PIO Write Cycle Timing
      • Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
      • Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
    • 15.5.10 Microwire Timing
      • Figure 15.10 Microwire Timing
      • Table 15.14 Microwire Timing Values
  • 15.6 Clock Circuit
    • Table 15.15 LAN9311/LAN9311iCrystal Specifications
• Chapter 16 Package Outlines
  • 16.1 128-VTQFP Package Outline
    • Figure 16.1 LAN9311 128-VTQFP Package Definition
    • Table 16.1 LAN9311 128-VTQFP Dimensions
    • Figure 16.2 LAN9311 128-VTQFP Recommended PCB Land Pattern
  • 16.2 128-XVTQFP Package Outline
    • Figure 16.3 LAN9311/LAN9311i 128-XVTQFP Package Definition
    • Table 16.2 LAN9311/LAN9311i 128-XVTQFP Dimensions
    • Figure 16.4 LAN9311/LAN9311i 128-XVTQFP Recommended PCB Land Pattern
• Chapter 17 Revision History
  • Table 17.1 Customer Revision History