Sharp ER-A440 - Manual (Page 18)

RAM area memory map
Fig. 5-4
Note: RAS2 signal is formed as OR in the image area of 0 page.
(lower32KB).
I/O area memory map
Fig. 5-5
Note 1: MPCCS signal is the base signal for MPCA7 internal reg-
isterdecoding, and does not exist as an internal signal.
Note 2: OPCCS1 and OPCCS2 signals are decoded in the OPC
(optionperipheral controller) using the base signal OPTCS
for optiondecoding. They does not exist as external sig-
nals.
2) Block diagram
Fig. 5-6
ROM control
Fig. 5-7
IPLON: IPL board detection signal incorporated in the option slot.
Note used in the ER-A445P. (Not used)
Access is performed with two ROM chip select signals ROS1 and
ROS2, which decode 512KB address area respectively to access-
max. 4MB ROM.
RAM control
Fig. 5-8
Access is performed with two RAM chip select signals, RAS2 and
RAS3. The control register in MPCA7 allows selection of pageimage
memory area. (RAS1 is selected for initializing.)
: For 0 page image area, selection between RAS2 and RAS3 can
bemade with the control register. The 0 page control registerper-
forms initializing at the timing of no stack processimmediately
after resetting.
100000H
400000H
BFFFFFH
NOT USE
NOT USE
RAS1 (Not use)
RAS2 64K Byte
RAS3
512K Byte
1C0000H
1F0000H
200000H
(MAX 2MB)
280000H
(OPTION)
00FF80H
00FFA0H
00FFFFH
MPCCS
NOT USE
NOT USE
NOT USE
OPCCS1
OPCCS2
00FFC0H
00FFD0H
00FFE0H
00FFF0H
(*1)
(*2)
(*2)
00FFE8H
MCR1 (NOT USE)
MCR2 (NOT USE)
NOT USE
CPU MPCA7
ROM1
(STANDARD)
RAM1
RAM2
(OPTION)
RAM
Data bus
Address bus
ROS1
RAS2 RAS3
Address
A23~A14
(IPLON)
Address
decorder
C80000H~CFFFFFH
C00000H~C7FFFFH
000000H~007FFFH
MPCA7
ROS2
ROS1
Address
A23~A14
Address
decorder
1C0000H~1DFFFFH
008000H~
00F7FFH
*1
1E0000H~1FFFFFH
RAS1
RAS2
RESET
D
CK
Q
R
DOI
S8F
Control register
MPCA7
RAS3
200000H~3FFFFFH
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