Renesas CPU Board M3A-HS19 - Manual (Page 26)

Features and Specifications
2.3.3 External Synchronous DRAM
Rev.1.01 Oct 28, .2008 2-10
REJ10J1351-0101
2
Figure 2.3.5 SDRAM Single Read/Write Timing
tAD1
tAD1
tAD1
tDQMD1
tRASD1
tRASD1
tCSD1
tHI
tSI
tSI
AC T
Tr Trw1
CKIO
CKE
CS3#
RAS#
CAS#
RD/WR#
DQMUU-LL
A11-A1(A9-A0)
A12(A10/AP)
A14,A13(BA1,0)
D15-0
SDRAM SINGLE READ
Data
tOHZ
tOH
tAC
tLZ
tAD1 tAD1 tAD1
tAD1 tAD1 tAD1
tAD1 tAD1 tAD1
tDQMD1 tDQMD1
tCASD1
tCASD1
tRASD1
tRASD1
tCSD1 tCSD1
tRDH2
tRDS2
tHI
tSI
tSI
tHI
tRC
tRP tRAS tRP
tRC
tRAS
READ A ACT
Tc1 Tcw Td1 Tde Tr Trw1 Tap
SDRAM SINGLE WRITE
tWDH2
tWDD2
tAD1 tAD1
tAD1 tAD1
tAD1 tAD1
tDQMD1
tRWD1
tRWD1
tCASD1
tCASD1
tCSD1
tHI
tSI
tHI
tDAL
tRP
tRC
tRP tRAS
tDPL
tDAL
tDPL
tRAS
tRC
W RITEA AC T
Tc1 Trwl1 Trwl2 Tr Tap
tRCD