8 sd host base address register, 9 subsystem vendor identification register – Texas Instruments Dual/Single Socket CardBus and UntraMedia Controller PCI7621 User Manual

Page 261

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12−7

12.8 SD Host Base Address Register

The SD host base address register specifies the base address of the memory-mapped interface registers for each
standard SD host socket. The size of each base address register (BAR) is 256 bytes. The number of BARs is
dependent on the number of SD sockets in the implementation See Table 12−7 for a complete description of the
register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

SD host base address

Type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

SD host base address

Type

RW

RW

RW

RW

RW

R

R

R

R

R

R

R

R

R

R

R

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Register:

SD host base address

Offset:

10h

Type:

Read/Write, Read-only

Default:

0000 0000h

Table 12−7. SD host Base Address Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31−8

BAR

RW

Base address. This field specifies the upper 24 bits of the 32-bit starting base address. The size of
the base address is 256 bytes.

7−4

RSVD

R

Reserved. Bits 7−4 return 0s when read.

3

PREFETCHABLE

R

Prefetchable indicator. This bit is hardwired to 0 to indicate that the memory space is not prefetchable.

2−1

TYPE

R

This field is hardwired to 00 to indicate that the base address is located in 32-bit address space.

0

MEM_INDICATOR

R

Memory space indicator. Bit 0 is hardwired to 0 to indicate that the base address maps into memory
space.

12.9 Subsystem Vendor Identification Register

The subsystem identification register, used for system and option card identification purposes, may be required for
certain operating systems. This read-only register is initialized through the EEPROM and can be written through the
subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register are reset by GRST only.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Subsystem vendor identification

Type

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Register:

Subsystem vendor identification

Offset:

2Ch

Type:

Read/Update

Default:

0000h

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