Texas Instruments SPRU938B - Manual (Page 21)

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VLYNQ interrupt
pending/set register
(INTPENDSET)
VLYNQ
Status/clear
register
(INTSTATCLR)
OR
Transmit serial
interrupt packet VLQINT
(INT55)
14 0
INTLOCAL
VLYNQ control register (CTRL)
Serial bus error
(LERROR/RERROR)
CPU writes
Serial interrupt
packet from
remote device
INTLOCAL=1
INTLOCAL=0
2.11.2 Writes to Interrupt Pending/Set Register
Peripheral Architecture
For additional flexibility of interrupt handling, the INSTAT bit in the interrupt priority vector status/clear
register (INTPRI) reports the highest priority interrupt asserted in INTPENDSET when INTLOCAL = 1 in
CTRL. The VLYNQ interprets bit 0 of the INSTAT bits as the highest priority and interprets bit 31 as the
lowest priority. The value that is returned when read is the vector of the highest priority interrupt. Software
can clear that interrupt by writing back the vector value. Additionally, INTRPRI provides a read-only status
bit (NOINTPEND) to indicate whether or not there are any pending interrupts in INTSTATCLR.
The VLYNQ interrupt generation mechanism is shown in Figure 8 .
Figure 8. Interrupt Generation Mechanism Block Diagram
As previously discussed, if the CPU writes to the VLYNQ interrupt pending/set register (INTPENDSET),
then depending on the value of the INTLOCAL bit in the VLYNQ control register (CTRL), this will result in
a local interrupt (to the device interrupt controller) or an interrupt packet transmitted over the serial
interface to the remote device.
SPRU938B – September 2007 VLYNQ Port 21
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