Texas Instruments TMS320C6454 - Manual

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PRODUCT PREVIEW
1 TMS320C6454 Fixed-Point Digital Signal Processor
1.1 Features
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
•
32-Bit DDR2 Memory Controller (DDR2-533 •
High-Performance Fixed-Point DSP (C6454)
SDRAM) – 1.39-, 1.17-, and 1-ns Instruction Cycle Time
•
EDMA3 Controller (64 Independent Channels) – 720-MHz, 850-MHz, and 1-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle •
32-/16-Bit Host-Port Interface (HPI)
– 8000 MIPS/MMACS (16-Bits) •
32-Bit 33-/66-MHz, 3.3-V Peripheral Component
– Commercial Temperature [0°C to 90°C] Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3
•
TMS320C64x+™ DSP Core
–
Dedicated SPLOOP Instruction •
One Inter-Integrated Circuit (I 2 C) Bus
– Compact Instructions (16-Bit) •
Two McBSPs
– Instruction Set Enhancements •
10/100/1000 Mb/s Ethernet MAC (EMAC)
– Exception Handling
– IEEE 802.3 Compliant
•
TMS320C64x+ Megamodule L1/L2 Memory
– Supports Multiple Media Independent
Architecture: Interfaces (MII, GMII, RMII, and RGMII)
– 256K-Bit (32K-Byte) L1P Program Cache – 8 Independent Transmit (TX) and
[Direct Mapped] 8 Independent Receive (RX) Channels
– 256K-Bit (32K-Byte) L1D Data Cache •
Two 64-Bit General-Purpose Timers,
[2-Way Set-Associative]
Configurable as Four 32-Bit Timers
– 8M-Bit (1048K-Byte) L2 Unified Mapped
•
16 General-Purpose I/O (GPIO) Pins
RAM/Cache [Flexible Allocation]
•
System PLL and PLL Controller
– 256K-Bit (32K-Byte) L2 ROM
•
Secondary PLL and PLL Controller, Dedicated
– Time Stamp Counter
to EMAC and DDR2 Memory Controller •
Endianess: Little Endian, Big Endian
•
IEEE-1149.1 (JTAG™) •
64-Bit External Memory Interface (EMIFA)
Boundary-Scan-Compatible
– Glueless Interface to Asynchronous
•
697-Pin Ball Grid Array (BGA) Package Memories (SRAM, Flash, and EEPROM) and
(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch Synchronous Memories (SBSRAM and ZBT
SRAM)
•
0.09-
µ
m/7-Level Cu Metal Process (CMOS)
– Supports Interface to Standard Sync •
3.3-/1.8-/1.5-V I/Os, 1.25-/1.2-V Internal
Devices and Custom Logic (FPGA, CPLD,
•
Pin-Compatible with the TMS320C6455
ASICs, etc.)
Fixed-Point Digital Signal Processor
– 32M-Byte Total Addressable External
Memory Space
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PRODUCT PREVIEW information concerns products in the Copyright © 2006–2006, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.