Texas Instruments TMS320C6454 - Manual (Page 50)

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PRODUCT PREVIEW
3 Device Configuration
3.1 Device Configuration at Device Reset
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
On the C6454 device, certain device configurations like boot mode, pin multiplexing, and endianess, are
selected at device reset. The status of the peripherals (enabled/disabled) is determined after device reset.
By default, the peripherals on the C6454 device are disabled and need to be enabled by software before
being used.
Table 3-1 describes the C6454 device configuration pins. The logic level of the AEA[19:0], ABA[1:0], and
PCI_EN pins is latched at reset to determine the device configuration. The logic level on the device
configuration pins can be set by using external pullup/pulldown resistors or by using some control device
(e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to
ensure there is no contention on the lines when the device is out of reset. The device configuration pins
are sampled during reset and are driven after the reset is removed. To avoid contention, the control device
should only drive the EMIFA pins when RESETSTAT is low.
NOTE
If a configuration pin must be routed out from the device and 3-stated (not driven), the
internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the
use of an external pullup/pulldown resistor. For more detailed information on
pullup/pulldown resistors and situations where external pullup/pulldown resistors are
required, see
Section 3.7 , Pullup/Pulldown Resistors.
Table 3-1. C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN)
CONFIGURATION IPD/
NO. FUNCTIONAL DESCRIPTION
PIN IPU (1)
Boot Mode Selections (BOOTMODE [3:0]).
These pins select the boot mode for the device.
0000 No boot (default mode)
0001 Host boot (HPI)
0010 Reserved
0011 Reserved
[N25, 0100 EMIFA 8-bit ROM boot
L26,
0101 Master I2C boot AEA[19:16] IPD
L25,
0110 Slave I2C boot P26]
0111 Host boot (PCI)
1000 thru Reserved
1111
If selected for boot, the corresponding peripheral is automatically enabled after device reset.
For more detailed information on boot modes, see
Section 2.4 , Boot Sequence.
CFGGP[2:0] pins must be set to 000b during reset for proper operation of the PCI boot
mode.
EMIFA input clock source select (AECLKIN_SEL).
0 AECLKIN (default mode)
AEA15 P27 IPD
1 SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software selectable
via the Software PLL1 Controller. By default, SYSCLK4 is selected as CPU/8
clock rate.
(1) IPD = Internal pulldown, IPU = Internal pullup. For most systems, a 1-k
Ω
resistor can be used to oppose the IPU/IPD. For more detailed
information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.7 ,
Pullup/Pulldown Resistors.
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