Texas Instruments TMS320C6454 - Manual (Page 216)

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PRODUCT PREVIEW
7.18 IEEE 1149.1 JTAG
7.18.1 JTAG Device-Specific Information
7.18.2 JTAG Peripheral Register Description(s)
7.18.3 JTAG Electrical Data/Timing
TCK
TDO
TDI/TMS/TRST
1
2
3
4
2
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
7.18.1.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6454 DSP includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be
properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive
TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of
an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the
DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan
operations.
Table 7-105. Timing Requirements for JTAG Test Port (see Figure 7-75 )
-720
-850
NO. UNIT
-1000
MIN MAX
1 t
c(TCK)
Cycle time, TCK 35 ns
3 t
su(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high 10 ns
4 t
h(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high 9 ns
Table 7-106. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 7-75 )
-720
-850
NO. PARAMETER UNIT
-1000
MIN MAX
2 t
d(TCKL-TDOV)
Delay time, TCK low to TDO valid -3 18 ns
Figure 7-75. JTAG Test-Port Timing
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