Texas Instruments TMS320C6454 - Manual (Page 126)

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PRODUCT PREVIEW
7.7.2 PLL1 Controller Memory Map
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1
with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The
PLL1 lock time is given in
Table 7-17 .
Table 7-17. PLL1 Stabilization, Lock, and Reset Times
MIN TYP MAX UNIT
PLL stabilization time 150
µ
s
PLL lock time 2000*C (1) ns
PLL reset time 128*C (1) ns
(1) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
The memory map of the PLL1 controller is shown in Table 7-18 . Note that only registers documented here
are accessible on the TMS320C6454. Other addresses in the PLL1 controller memory map should not be
modified.
Table 7-18. PLL1 Controller Registers (Including Reset Controller)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
029A 0000 - 029A 00E3 - Reserved
029A 00E4 RSTYPE Reset Type Status Register (Reset Controller)
029A 00E8 - 029A 00FF - Reserved
029A 0100 PLLCTL PLL Control Register
029A 0104 - Reserved
029A 0108 - Reserved
029A 010C - Reserved
029A 0110 PLLM PLL Multiplier Control Register
029A 0114 PREDIV PLL Pre-Divider Control Register
029A 0118 - Reserved
029A 011C - Reserved
029A 0120 - Reserved
029A 0124 - Reserved
029A 0128 - Reserved
029A 012C - Reserved
029A 0130 - Reserved
029A 0134 - Reserved
029A 0138 PLLCMD PLL Controller Command Register
029A 013C PLLSTAT PLL Controller Status Register
029A 0140 ALNCTL PLL Controller Clock Align Control Register
029A 0144 DCHANGE PLLDIV Ratio Change Status Register
029A 0148 - Reserved
029A 014C - Reserved
029A 0150 SYSTAT SYSCLK Status Register
029A 0154 - Reserved
029A 0158 - Reserved
029A 015C - Reserved
029A 0160 PLLDIV4 PLL Controller Divider 4 Register
029A 0164 PLLDIV5 PLL Controller Divider 5 Register
029A 0168 - 029B FFFF - Reserved
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