Texas Instruments TMS320C6454 - Manual (Page 119)

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PRODUCT PREVIEW
7.6.5 Reset Priority
7.6.6 Reset Controller Register
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority
reset request. The rest request priorities are as follows (high to low):
•
Power-on Reset
•
Maximum Reset
•
Warm Reset
•
System Reset
•
CPU Reset
The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This
register falls in the same memory range as the PLL1 controller registers [029A 0000 - 029A 01FF] (see
Table 7-18 ).
7.6.6.1 Reset Type Status Register Description
The rest type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The reset type status register is
shown in
Figure 7-7 and described in Table 7-13 .
31 16
Reserved
R-0
15 4 3 2 1 0
Reserved SRST Rsvd WRST POR
R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-7. Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4]
Table 7-13. Reset Type Status Register (RSTYPE) Field Descriptions
Bit Field Value Description
31:4 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
3 SRST System reset.
0 System Reset was not the last reset to occur.
1 System Reset was the last reset to occur.
2 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
1 WRST Warm reset.
0 Warm Reset was not the last reset to occur.
1 Warm Reset was the last reset to occur.
0 POR Power-on reset.
0 Power-on Reset was not the last reset to occur.
1 Power-on Reset was the last reset to occur.
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