Texas Instruments TMS320C6454 - Manual (Page 133)

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PRODUCT PREVIEW
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
7.7.3.7 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in
Figure 7-17 and described in Table 7-25 .
31 16
Reserved
R-0
15 1 0
Reserved GOSTAT
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-17. PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C]
Table 7-25. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit Field Value Description
31:1 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0 GOSTAT GO operation status.
0 GO operation is not in progress. SYSCLK divide ratios are not being changed.
1 GO operation is in progress. SYSCLK divide ratios are being changed.
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