Texas Instruments TMS320C6454 - Manual (Page 5)

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PRODUCT PREVIEW
Contents
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
1 TMS320C6454 Fixed-Point Digital Signal 5.5 Megamodule Resets
................................
81
Processor
..................................................
1
5.6 Megamodule Revision
...............................
82
1.1 Features
..............................................
1
5.7 C64x+ Megamodule Register Description(s)
........
83
1.1.1 ZTZ/GTZ BGA Package (Bottom View)
..............
2 6 Device Operating Conditions ........................ 90
1.2 Description
............................................
2 6.1 Absolute Maximum Ratings Over Operating Case
Temperature Range (Unless Otherwise Noted)
.....
90 1.3 Functional Block Diagram
............................
4
6.2 Recommended Operating Conditions
...............
90 2 Device Overview ......................................... 6
6.3 Electrical Characteristics Over Recommended 2.1 Device Characteristics
................................
6
Ranges of Supply Voltage and Operating Case
2.2 CPU (DSP Core) Description
.........................
7
Temperature (Unless Otherwise Noted)
............
92
2.3 Memory Map Summary
.............................
10
7 C64x+ Peripheral Information and Electrical
2.4 Boot Sequence
......................................
12 Specifications ........................................... 94
2.5 Pin Assignments
....................................
14
7.1 Parameter Information
..............................
94
2.6 Signal Groups Description
..........................
18 7.2 Recommended Clock and Control Signal Transition
Behavior
.............................................
96 2.7 Terminal Functions
..................................
24
7.3 Power Supplies
......................................
96 2.8 Development
........................................
47
7.4 Enhanced Direct Memory Access (EDMA3) 3 Device Configuration .................................. 50
Controller
............................................
98
3.1 Device Configuration at Device Reset
..............
50
7.5 Interrupts
...........................................
112
3.2 Peripheral Configuration at Device Reset
...........
52
7.6 Reset Controller
....................................
116
3.3 Peripheral Selection After Device Reset
............
53
7.7 PLL1 and PLL1 Controller
.........................
123
3.4 Device State Control Registers
.....................
55
7.8 PLL2 and PLL2 Controller
.........................
138
3.5 Device Status Register Description
.................
65
7.9 DDR2 Memory Controller
..........................
147
3.6 JTAG ID (JTAGID) Register Description
............
67
7.10 External Memory Interface A (EMIFA)
.............
149
3.7 Pullup/Pulldown Resistors
...........................
67
7.11 I2C Peripheral
......................................
160
3.8 Configuration Examples
.............................
69
7.12 Host-Port Interface (HPI) Peripheral
...............
166
4 System Interconnect ................................... 71
7.13 Multichannel Buffered Serial Port (McBSP)
........
177
4.1 Internal Buses, Bridges, and Switch Fabrics
........
71
7.14 Ethernet MAC (EMAC)
.............................
187
4.2 Data Switch Fabric Connections
....................
72
7.15 Timers
..............................................
205
4.3 Configuration Switch Fabric
.........................
74
7.16 Peripheral Component Interconnect (PCI)
.........
207
4.4 Priority Allocation
....................................
76
7.17 General-Purpose Input/Output (GPIO)
.............
214
5 C64x+ Megamodule .................................... 77
7.18 IEEE 1149.1 JTAG
.................................
216
5.1 Memory Architecture
................................
77
8 Mechanical Data
.......................................
217
5.2 Memory Protection
..................................
80
8.1 Thermal Data
......................................
217
5.3 Bandwidth Management
............................
80
8.2 Packaging Information
.............................
217
5.4 Power-Down Control
................................
81
Revision History
............................................
218
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