Document Outline

• 1 TMS320C6454 Fixed-Point Digital Signal Processor
  • 1.1 Features
  • 1.1.1 ZTZ/GTZ BGA Package (Bottom View)
  • 1.2 Description
  • 1.3  Functional Block Diagram
• Table of Contents
• 2 Device Overview
  • 2.1 Device Characteristics
  • 2.2 CPU (DSP Core) Description
  • 2.3 Memory Map Summary
  • 2.4 Boot Sequence
    • 2.4.1 Boot Modes Supported
    • 2.4.2 2nd-Level Bootloaders
  • 2.5 Pin Assignments
    • 2.5.1 Pin Map
  • 2.6 Signal Groups Description
  • 2.7 Terminal Functions
  • 2.8 Development
    • 2.8.1 Development Support
    • 2.8.2 Device Support
• 3 Device Configuration
  • 3.1 Device Configuration at Device Reset
  • 3.2 Peripheral Configuration at Device Reset
  • 3.3 Peripheral Selection After Device Reset
  • 3.4 Device State Control Registers
    • 3.4.1 Peripheral Lock Register Description
    • 3.4.2 Peripheral Configuration Register 0 Description
    • 3.4.3 Peripheral Configuration Register 1 Description
    • 3.4.4 Peripheral Status Registers Description
    • 3.4.5 EMAC Configuration Register (EMACCFG) Description
    • 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description
  • 3.5 Device Status Register Description
  • 3.6 JTAG ID (JTAGID) Register Description
  • 3.7 Pullup/Pulldown Resistors
  • 3.8 Configuration Examples
• 4 System Interconnect
  • 4.1 Internal Buses, Bridges, and Switch Fabrics
  • 4.2 Data Switch Fabric Connections
  • 4.3 Configuration Switch Fabric
  • 4.4 Priority Allocation
• 5 C64x+ Megamodule
  • 5.1 Memory Architecture
  • 5.2 Memory Protection
  • 5.3 Bandwidth Management
  • 5.4 Power-Down Control
  • 5.5 Megamodule Resets
  • 5.6 Megamodule Revision
  • 5.7 C64x+ Megamodule Register Description(s)
• 6 Device Operating Conditions
  • 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
  • 6.2 Recommended Operating Conditions
  • 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
• 7 C64x+ Peripheral Information and Electrical Specifications
  • 7.1 Parameter Information
    • 7.1.1  3.3-V Signal Transition Levels
    • 7.1.2  3.3-V Signal Transition Rates
    • 7.1.3  Timing Parameters and Board Routing Analysis
  • 7.2 Recommended Clock and Control Signal Transition Behavior
  • 7.3 Power Supplies
    • 7.3.1 Power-Supply Sequencing
    • 7.3.2 Power-Supply Decoupling
    • 7.3.3 Power-Down Operation
    • 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins
  • 7.4 Enhanced Direct Memory Access (EDMA3) Controller
    • 7.4.1 EDMA3 Device-Specific Information
    • 7.4.2 EDMA3 Channel Synchronization Events
    • 7.4.3 EDMA3 Peripheral Register Description(s)
  • 7.5 Interrupts
    • 7.5.1 Interrupt Sources and Interrupt Controller
    • 7.5.2  External Interrupts Electrical Data/Timing
  • 7.6 Reset Controller
    • 7.6.1 Power-on Reset (POR Pin)
    • 7.6.2 Warm Reset (RESET Pin)
    • 7.6.3 System Reset
    • 7.6.4 CPU Reset
    • 7.6.5 Reset Priority
    • 7.6.6 Reset Controller Register
    • 7.6.7 Reset Electrical Data/Timing
  • 7.7 PLL1 and PLL1 Controller
    • 7.7.1 PLL1 Controller Device-Specific Information
    • 7.7.2 PLL1 Controller Memory Map
    • 7.7.3 PLL1 Controller Register Descriptions
    • 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing
  • 7.8 PLL2 and PLL2 Controller
    • 7.8.1 PLL2 Controller Device-Specific Information
    • 7.8.2 PLL2 Controller Memory Map
    • 7.8.3 PLL2 Controller Register Descriptions
    • 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing
  • 7.9 DDR2 Memory Controller
    • 7.9.1 DDR2 Memory Controller Device-Specific Information
    • 7.9.2 DDR2 Memory Controller Peripheral Register Description(s)
    • 7.9.3 DDR2 Memory Controller Electrical Data/Timing
  • 7.10 External Memory Interface A (EMIFA)
    • 7.10.1 EMIFA Device-Specific Information
    • 7.10.2 EMIFA Peripheral Register Description(s)
    • 7.10.3 EMIFA Electrical Data/Timing
    • 7.10.4 HOLD/HOLDA Timing
    • 7.10.5 BUSREQ Timing
  • 7.11 I2C Peripheral
    • 7.11.1 I2C Device-Specific Information
    • 7.11.2 I2C Peripheral Register Description(s)
    • 7.11.3 I2C Electrical Data/Timing
  • 7.12 Host-Port Interface (HPI) Peripheral
    • 7.12.1 HPI Device-Specific Information
    • 7.12.2 HPI Peripheral Register Description(s)
    • 7.12.3 HPI Electrical Data/Timing
  • 7.13 Multichannel Buffered Serial Port (McBSP)
    • 7.13.1 McBSP Device-Specific Information
    • 7.13.2 McBSP Electrical Data/Timing
  • 7.14 Ethernet MAC (EMAC)
    • 7.14.1 EMAC Device-Specific Information
    • 7.14.2 EMAC Peripheral Register Description(s)
    • 7.14.3 EMAC Electrical Data/Timing
    • 7.14.4  Management Data Input/Output (MDIO)
  • 7.15 Timers
    • 7.15.1 Timers Device-Specific Information
    • 7.15.2 Timers Peripheral Register Description(s)
    • 7.15.3 Timers Electrical Data/Timing
  • 7.16 Peripheral Component Interconnect (PCI)
    • 7.16.1 PCI Device-Specific Information
    • 7.16.2 PCI Peripheral Register Description(s)
    • 7.16.3 PCI Electrical Data/Timing
  • 7.17 General-Purpose Input/Output (GPIO)
    • 7.17.1 GPIO Device-Specific Information
    • 7.17.2 GPIO Peripheral Register Description(s)
    • 7.17.3 GPIO Electrical Data/Timing
  • 7.18 IEEE 1149.1 JTAG
    • 7.18.1 JTAG Device-Specific Information
    • 7.18.2 JTAG Peripheral Register Description(s)
    • 7.18.3 JTAG Electrical Data/Timing
• 8 Mechanical Data
  • 8.1 Thermal Data
  • 8.2 Packaging Information
• Revision History