Texas Instruments TMS320DM646X DMSOC - Manual (Page 56)

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4.6 EMIF Interrupt Mask Set Register (EIMSR)
The EMIF interrupt mask set register (EIMSR) is used to enable the interrupts. If a bit is set to 1, the
corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the
associated interrupt condition occurs. If a bit is cleared to 0, the the corresponding bit in EIMR will always
read 0 and no interrupts are generated when the associated interrupt condition occurs. Writing a 1 to the
WRMSETn and ATMSET bits enables each respective interrupt. The EIMSR is shown in
Figure 25 and
described in Table 38 .
Figure 25. EMIF Interrupt Mask Set Register (EIMSR)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved WRMSET3 WRMSET2 WRMSET1 WRMSET0 Reserved ATMSET
R-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R-0 R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing 0 has no effect); -n = value after reset
Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
5 WRMSET3 Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the
WRMCLR3 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To
clear this bit, a 1 must be written to the WRMCLR3 bit in EIMCR.
0 Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
1 Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR3 bit in
EIMCR.
4 WRMSET2 Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the
WRMCLR2 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To
clear this bit, a 1 must be written to the WRMCLR2 bit in EIMCR.
0 Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
1 Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR2 bit in
EIMCR.
3 WRMSET1 Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the
WRMCLR1 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To
clear this bit, a 1 must be written to the WRMCLR1 bit in EIMCR.
0 Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
1 Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR1 bit in
EIMCR.
2 WRMSET0 Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the
WRMCLR0 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To
clear this bit, a 1 must be written to the WRMCLR0 bit in EIMCR.
0 Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
1 Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR0 bit in
EIMCR.
1 Reserved 0 Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
56 Asynchronous External Memory Interface (EMIF) SPRUEQ7C – February 2010
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