Texas Instruments TMS320C6202 - Manual (Page 45)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
45
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EXPANSION BUS SYNCHRONOUS FIFO TIMING
timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)
NO. MIN MAX UNIT
5 tsu(XDV-XFCKH) Setup time, read XDx valid before XFCLK high 2.5 ns
6 th(XFCKH-XDV) Hold time, read XDx valid after XFCLK high 2 ns
switching characteristics for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)
NO. PARAMETER MIN MAX UNIT
1 td(XFCKH-XCEV) Delay time, XFCLK high to XCEx valid 1.5 5.2 ns
2 td(XFCKH-XAV) Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid† 1.5 5.2 ns
3 td(XFCKH-XOEV) Delay time, XFCLK high to XOE valid 1.5 5.2 ns
4 td(XFCKH-XREV) Delay time, XFCLK high to XRE valid 1.5 5.2 ns
7 td(XFCKH-XWEV) Delay time, XFCLK high to XWE/XWAIT‡ valid 1.5 5.2 ns
8 td(XFCKH-XDV) Delay time, XFCLK high to XDx valid 5.2 ns
9 td(XFCKH-XDIV) Delay time, XFCLK high to XDx invalid 1.5 ns
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
XA1 XA2 XA3 XA4
D1 D2 D3 D4
6
5
4 4
3 3
2 2
1 1
XFCLK
XCE3†
XBE[3:0]/XA[5:2]‡
XOE
XRE
XWE/XWAIT§
XD[31:0]
† FIFO read (glueless) mode only available in XCE3.
‡ XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
§ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
Figure 26. FIFO Read Timing (Glueless Read Mode)
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