Texas Instruments TMS320C6202 - Manual (Page 55)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
55
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EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING
timing requirements with external device as asynchronous bus master † (see Figure 36 and
Figure 37)
NO. MIN MAX UNIT
1 tw(XCSL) Pulse duration, XCS low 4P ns
2 tw(XCSH) Pulse duration, XCS high 4P ns
3 tsu(XSEL-XCSL) Setup time, expansion bus select signals‡ valid before XCS low 2 ns
4 th(XCSL-XSEL) Hold time, expansion bus select signals‡ valid after XCS low 2 ns
10 th(XRYL-XCSL) Hold time, XCS low after XRDY low P ns
11 tsu(XBEV-XCSH) Setup time, XBE[3:0]/XA[5:2] valid before XCS high§ 2 ns
12 th(XCSH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCS high§ 2 ns
13 tsu(XDV-XCSH) Setup time, XDx valid before XCS high 2 ns
14 th(XCSH-XDV) Hold time, XDx valid after XCS high 2 ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ Expansion bus select signals include XCNTL and XR/W.
§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
switching characteristics with external device as asynchronous bus master (see Figure 36 and
Figure 37)
NO. PARAMETER MIN MAX UNIT
5 td(XCSL-XDLZ) Delay time, XCS low to XDx low impedance 0 ns
6 td(XCSH-XDIV) Delay time, XCS high to XDx invalid 0 12 ns
7 td(XCSH-XDHZ) Delay time, XCS high to XDx high impedance 12 ns
8 td(XRYL-XDV) Delay time, XRDY low to XDx valid 0 4 ns
9 td(XCSH-XRYH) Delay time, XCS high to XRDY high 0 12 ns
Word
9 9
7
6 8 5
7
6
8 5
4
3
4
3
4
3
4
3
4
3
4
3
XCS
XCNTL
XBE[3:0]/XA[5:2]†
XR/W‡
XR/W‡
XD[31:0]
XRDY
10
1
2
1
10
† XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
‡ XW/R input/output polarity selected at boot
Figure 36. External Device as Asynchronous Master—Read
ADV
ANCE INFORMA
TION