Rainbow Electronics MAX6869 - Manual (Page 11)

MAX6854–MAX6869
Nanopower µP Supervisory Circuits with
Optional Manual Reset, Watchdog Timer
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Detailed Description
RESET
/RESET Output
A µP’s reset input starts the µP in a known state. The
MAX6854–MAX6869 µP supervisory circuits assert a
reset to prevent code-execution errors during power-
up, power-down, and brownout conditions. The
MAX6854–MAX6869 reset output is guaranteed to be
valid for V
CC down to 1.1V.
Whenever V CC falls below the reset threshold, the reset
output asserts low for RESET and high for RESET.
Once V
CC exceeds the reset threshold, an internal
timer keeps the reset output asserted for the specified
reset timeout period, then after this interval the reset
output deasserts (see
Figure 2).
Manual Reset Input
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. The MAX6854/
MAX6855/MAX6856/MAX6861–MAX6869 feature an
MR input. A logic low on MR asserts a reset. Reset
remains asserted while MR is low and for the timeout
period, t
RP
, after MR returns high. The devices provide
an internal 10kΩ pullup from MR to V CC . Leave MR
unconnected or connect to V CC if unused. MR can be
driven with CMOS logic levels or with open-drain/col-
lector outputs. Connect a normally open momentary
switch from MR to GND to implement a manual reset
function; external debounce circuitry is not required. If
MR is driven by long cables or the device is used in a
noisy environment, connect a 0.1µF capacitor from MR
to GND to provide additional noise immunity.
Watchdog Input
The MAX6864–MAX6869’s watchdog timer circuitry
monitors the µP’s activity. If the µP does not toggle
(low-to-high or high-to-low) the watchdog input (WDI)
within the watchdog timeout period (t
WDI ), reset asserts
for the reset timeout period (t
RP
). The internal timer is
cleared when reset asserts, when manual reset is
asserted, or by a rising or falling edge on WDI. The
watchdog input detects pulses as short as 150ns.
While reset is asserted the watchdog timer does not
count. As soon as reset deasserts, the watchdog timer
resumes counting (
Figure 3).
Applications Information
Selecting the Reset Timeout Period
The reset timeout period for the MAX6854–
MAX6860/MAX6864–MAX6869 is fixed (see
Table 4).
The MAX6861/MAX6862/MAX6863 feature a reset time-
out select input, CT. Connect CT according to
Table 1
to select between the available 10ms and 150ms (min)
reset timeout periods. The timeout period can be
changed while a reset timeout period is in progress,
but will not update until the reset timeout period has
expired.
V CC
WDI t WD t WDI
t RP
RESET*
V CC
OV
OV
*RESET IS THE INVERSE OF RESET.
Figure 3. Detailed Watchdog Input Timing Relationship
Table 1. MAX6861/MAX6862/MAX6863
Reset Timeout Period Selection
CT CONNECTION MIN TYP MAX UNITS
LOW 10 15 25
HIGH 150 225 300
ms