Rainbow Electronics W90N740 - Manual (Page 45)

W90N740
Publication Release Date: November 26, 2004
- 41 - Revision A4
7.3.3 External Bus Mastership
The W90N740 can receive and acknowledge bus request signals that are generated by an external bus
master. When the CPU asserts an external bus acknowledge signal, mastership is granted to the
external bus master, assuming the external bus request is still active.
When the external bus acknowledge signal is active, the W90N740’s memory interface signals go to high
impedance state so that the external bus master can drive the required external memory interface
signals.
The W90N740 does not perform SDRAM refreshes when it is not the bus master. When an external bus
master is in control of the external bus, and if it retains control for a long period of time, it must assume
the responsibility of performing the necessary SDRAM refresh operations.
7.3.4 EBI Control Registers Map
Register Address R/W Description Reset Value
EBICON 0xFFF0.1000 R/W EBI control register 0x0001.0000
ROMCON 0xFFF0.1004 R/W ROM/FLASH control register 0x0000.0XFC
SDCONF0 0xFFF0.1008 R/W SDRAM bank 0 configuration register 0x0000.0800
SDCONF1 0xFFF0.100C R/W SDRAM bank 1 configuration register 0x0000.0800
SDTIME0 0xFFF0.1010 R/W SDRAM bank 0 timing control register 0x0000.0000
SDTIME1 0xFFF0.1014 R/W SDRAM bank 1 timing control register 0x0000.0000
EXT0CON 0xFFF0.1018 R/W External I/O 0 control register 0x0000.0000
EXT1CON 0xFFF0.101C R/W External I/O 1 control register 0x0000.0000
EXT2CON 0xFFF0.1020 R/W External I/O 2 control register 0x0000.0000
EXT3CON 0xFFF0.1024 R/W External I/O 3 control register 0x0000.0000
CKSKEW 0xFFF0.1F00 R/W Clock skew control register 0xXXXX.0038