Rainbow Electronics MAX8707 - Manual (Page 16)

MAX8707
Detailed Description
+5V Bias Supply (V CC )
The MAX8707 requires an external +5V bias supply in
addition to the battery. Typically, this +5V bias supply is
the notebook’s 95%-efficient, +5V system supply.
Keeping the bias supply external to the controller
improves efficiency and eliminates the cost associated
with the +5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the +5V bias supply
can be generated with an external linear regulator.
The +5V bias supply must provide V CC (PWM con-
troller) and V DRV (FET gate-drive power), so the maxi-
mum current drawn is:
I BIAS = I CC + I DRIVE
where I CC is provided in the Electrical Characteristics
table and I
DRIVE
is the driver’s supply current dominat-
ed by f SW x Q G (per phase) as defined in the driver’s
data sheet. If the +5V bias supply is powered up prior
to the battery supply, the enable signal (SHDN going
from low to high) must be delayed until the battery volt-
age is present to ensure startup.
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
16 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
30 CRSP
Positive Current-Sense Resistor Input. CRSP is the positive differential input used for accurate sensing of
the phase 1 inductor current. Connect a current-sense resistor between CRSP and CRSN. If current-sense
resistors are used on all phases (CSP_, CSN_), this additional current-sense (CRSP, CRSN) feature can be
disabled by connecting CRSP to V
CC and floating CRSN.
31 CSP1
Positive Current-Sense Input for Phase 1. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
32 CSN1 Negative Current-Sense Input for Phase 1
33 CSN2 Negative Current-Sense Input for Phase 2
34 CSP2
Positive Current-Sense Input for Phase 2. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
35 CSP3
Positive Current-Sense Input for Phase 3. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
36 CSN3 Negative Current-Sense Input for Phase 3
37 CSN4 Negative Current-Sense Input for Phase 4
38 CSP4
Positive Current-Sense Input for Phase 4. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented. Connect CSP4 to V
CC for fixed 3-phase operation.
39 D0
Low-Voltage VID-DAC Code Inputs. The D0–D4 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = low), the output
voltage is set by the D0–D4 VID-DAC inputs. In suspend mode (SUS = high), the output voltage tracks the
voltage at SUSV.
40 D1 Low-Voltage VID-DAC Code Inputs