Rainbow Electronics MAX8707 User Manual
Page 28
MAX8707
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
28
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DRIVER
INPUT (V
IN
)
C
IN
D
L
C
OUT
L
R
SENSE
N
H
N
L
CONTROLLER
DH
DL
PGND
CSP_
CSN_
PWM
PWM_
LX
A) OUTPUT SERIES RESISTOR SENSING
DRIVER
INPUT (V
IN
)
C
IN
D
L
C
OUT
L
R
DCR
N
H
N
L
CONTROLLER
DH
DL
PGND
CSP_
CSN_
PWM
PWM_
LX
B) LOSSLESS INDUCTOR SENSING
INDUCTOR
R
EQ
C
SENSE
Figure
7. Current-Sense Methods
Power-Up Sequence (POR, UVLO)
Power-on reset (POR) occurs when V
CC
rises above
approximately 2V, resetting the fault latch and prepar-
ing the controller for operation. The V
CC
undervoltage-
lockout (UVLO) circuitry inhibits switching—forces
DRSKP high and pulls the PWM_ outputs low—until
V
CC
rises above 4.25V. The controller powers up the
reference once the system enables the controller—V
CC
above 4.25V and SHDN pulled high. With the reference
in regulation, the controller begins to slew the output
voltage to the target voltage—either the output of the
VID DAC (SUS = low) or the SUSV suspend voltage
(SUS = high)—at 1/4th the slew rate set by R
TIME
:
where dV
TARGET
/ dt = 6.25mV/µs
× 143kΩ / R
TIME
is the
slew rate. The soft-start circuitry does not use a variable
current limit, so full output current is available immediate-
ly. VROK becomes high impedance approximately 20µs
after the MAX8707 reaches the target voltage.
For automatic startup, the battery voltage should be
present before V
CC
. If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
or cycling the V
CC
power supply below 1V.
If the V
CC
voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, the controller shuts down immediately—
forces DRSKP high and pulls the PWM_ outputs low.
Shutdown
When SHDN goes low, the MAX8707 enters low-power
shutdown mode. VROK is pulled low immediately, and
the output voltage ramps down at 1/4th the slew rate
set by R
TIME
:
where dV
TARGET
/ dt = 6.25mV/µs
× 143kΩ / R
TIME
is
the slew rate. Slowly discharging the output capacitors
by slewing the output over a long period of time keeps
the average negative inductor current low (damped
response), thereby eliminating the negative output volt-
age excursion that occurs when the controller dis-
charges the output quickly by permanently turning on
the low-side MOSFET (underdamped response). This
eliminates the need for the Schottky diode normally
connected between the output and ground to clamp
t
V
dV
dt
TRAN SHDN
OUT
TARGET
(
)
/
=
4
t
V
dV
dt
TRAN START
TARGET
TARGET
(
)
/
=
4