Table 3. system register bit and reset values – Rainbow Electronics MAXQ7670 User Manual

Page 31

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MAXQ7670

Microcontroller with 10-Bit ADC,

PGA, 64KB Flash, and CAN Interface

______________________________________________________________________________________

31

REGISTER BIT

REGISTER

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

AP (4 Bits)

AP

0

0

0

0

0

0

0

0

CLR

IDS

MOD2

MOD1

MOD0

APC

0

0

0

0

0

0

0

0

Z

S

GPF1

GPF0

OV

C

E

PSF

1

0

0

0

0

0

0

0

CGDS

INS

IGE

IC

0

0

0

0

0

0

0

0

IMS

IM5

IM4

IM3

IM2

IM1

IM0

IMR

0

0

0

0

0

0

0

0

TAP

CDA1

CDA0

UPA

ROD

PWL

SC

1

0

0

0

0

0

s*

0

IIS

II5

II4

II3

II2

II1

II0

IIR

0

0

0

0

0

0

0

0

XT

RGMD

STOP

SWB

PMME

CD1

CD0

CKCN

s*

0

s*

0

0

0

0

1

POR

EWDI

WD1

WD0

WDIF

WTRF

EWT

RWT

WDCN

s*

s*

0

0

0

s*

s*

0

A[n] (16 Bits)

A[n] (0..15)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PFX[n] (16 Bits)

PFX[n] (0..15)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

IP (16 Bits)

IP

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SP (4 Bits)

SP

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

IV (16 Bits)

IV

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

LC[0] (16 Bits)

LC[0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

LC[1] (16 Bits)

LC[1]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

OFFS (8 Bits)

OFFS

0

0

0

0

0

0

0

0

WBS2

WBS1

WBS0

SDPS1

SDPS0

DPC

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

GR.15

GR.14

GR.13

GR.12

GR.11

GR.10

GR.9

GR.8

GR.7

GR.6

GR.5

GR.4

GR.3

GR.2

GR.1

GR.0

GR

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

GR.7

GR.6

GR.5

GR.4

GR.3

GR.2

GR.1

GR.0

GRL

0

0

0

0

0

0

0

0

BP (16 Bits)

BP

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

GR.7

GR.6

GR.5

GR.4

GR.3

GR.2

GR.1

GR.0

GR.15

GR.14

GR.13

GR.12

GR.11

GR.10

GR.9

GR.8

GRS

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

GR.15

GR.14

GR.13

GR.12

GR.11

GR.10

GR.9

GR.8

GRH

0

0

0

0

0

0

0

0

GR.7

GR.7

GR.7

GR.7

GR.7

GR.7

GR.7

GR.7

GR.7

GR.6

GR.5

GR.4

GR.3

GR.2

GR.1

GR.0

GRXL

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FP (16 Bits)

FP

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DP[0] (16 Bits)

DP[0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DP[1] (16 Bits)

DP[1]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Table 3. System Register Bit and Reset Values

*Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the
MAXQ7670 User’s Guide for more information.

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