Rainbow Electronics ADC1061 - Manual (Page 7)

Pin Descriptions
(Continued)
Symbol Function
GND (10) This is the power supply ground pin The
ground pin should be connected to a
‘‘clean’’ ground reference point
DB0 – DB9 These are the TRI-STATE output pins
(11-20)
Functional Description
The ADC1061 digitizes an analog input signal to 10 bits ac-
curacy by performing two lower-resolution ‘‘flash’’ conver-
sions The first flash conversion provides the six most signif-
icant bits (MSBs) of data and the second flash conversion
provides the four least significant bits (LSBs)
Figure 3 is a simplified block diagram of the converter Near
the center of the diagram is a string of resistors At the
bottom of the string of resistors are 16 resistors each of
which has a value 1 1024th the resistance of the whole
resistor string These lower 16 resistors (the LSB Ladder)
therefore have a voltage drop of 16 1024 or 1 64th of the
total reference voltage (V
REF a b VREFb) across them
The remainder of the resistor string is made up of eight
groups of eight resistors connected in series These com-
prise the MSB Ladder Each section of the MSB Ladder
has 1 8th of the total reference voltage across it and each
of the MSB resistors has 1 64th of the total reference volt-
age across it Tap points across all of these resistors can be
connected in groups to the sixteen comparators at the
right of the diagram
On the left side of the diagram is a string of seven resistors
connected between V
REF a b V REF b
Six comparators
compare the input voltage with the tap voltages on the re-
sistor string to provide an estimate of the input voltage This
estimate is then used to control the multiplexer that con-
nects the MSB Ladder to the sixteen comparators on the
right Note that the comparators on the left needn’t be very
accurate they simply provide an estimate of the input volt-
age Only the sixteen comparators on the right and the six
on the left are necessary to perform the initial six-bit flash
conversion instead of the 64 comparators that would be
required using conventional half-flash methods
To perform a conversion the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left The estimator decoder then determines which MSB
Ladder tap points will be connected to the sixteen compara-
tors on the right For example assume that the estimator
determines that V
IN is between 11 16 and 13 16 of VREF
The estimator decoder will instruct the comparator mux to
connect the 16 comparators to the taps on the MSB Ladder
between 10 16 and 14 16 of VREF The 16 comparators
will then perform the first flash conversion Note that since
the comparators are connected to Ladder voltages that ex-
tend beyond the range indicated by the estimator circuit
errors in the estimator as large as
of the reference volt-
age (64 LSBs) will be corrected This first flash conversion
produces the six most significant bits of data
TL H 10559 – 13
FIGURE 3 Block Diagram of the Modified Half-Flash Converter Architecture
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