Rainbow Electronics MAX9768 User Manual
Page 16
MAX9768
10W Mono Class D Speaker
Amplifier with Volume Control
16
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Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions
section). SDA and SCL idle high when the
I
2
C bus is not busy.
START and STOP Conditions
A master device initiates communication by issuing a
START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure 4).
A START (S) condition from the master signals the
beginning of a transmission to the MAX9768. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP (P) condition. The bus remains active if a
REPEATED START (Sr) condition is generated instead
of a STOP condition.
Early STOP Conditions
The MAX9768 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Slave Address
The slave address of the MAX9768 is 8 bits and con-
sisting of 3 fields: the first field is 5 bits wide and is
fixed (10010). The second is a 2-bit field, which is set
through ADDR2 and ADDR1 (externally connected as
logic-high or low). Third field is a R/
W flag bit. Set R/W
= 0 to write to the slave. A representation of the slave
address is shown in Table 3.
When ADDR1 and ADDR2 are connected to GND, seri-
al interface communication is disabled. Table 4 sum-
marizes the slave address of the device as a function of
ADDR1 and ADDR2.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9768 uses to handshake receipt each byte of data
(Figure 5). The MAX9768 pulls down SDA during the
master-generated 9th clock pulse. The SDA line must
remain stable and low during the high period of the
acknowledge clock pulse. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master can re-
attempt communication.
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
t
HD,STA
t
SU,STA
t
HD,STA
t
SP
t
BUF
t
SU,STO
t
LOW
t
SU,DAT
t
HD,DAT
t
HIGH
t
R
t
F
Figure 3. 2-Wire Serial-Interface Timing Diagram
SCL
SDA
S
Sr
P
Figure 4. START, STOP, and REPEATED START Conditions