registers, Preliminary, Registers – Rainbow Electronics T89C51CC02 User Manual

Page 81

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Rev.A - May 17, 2001

81

Preliminary

T89C51CC02

15.12. Registers

CANGCON (S:ABh)
CAN General Control Register

Reset Value: 0000 0x00b

Figure 65. CANGCON Register

7

6

5

4

3

2

1

0

ABRQ

OVRQ

TTC

SYNCTTC

AUTOBAUD

TEST

ENA

GRES

Bit Number Bit Mnemonic

Description

7

ABRQ

Abort request

Not an auto-resettable bit. A reset of the ENCH bit (message object control & DLC register) is done
for each message object. The pending communications are immediately disabled and the on-going
communication will be terminated normally, setting the appropriate status flags, TXOK or RXOK.

6

OVRQ

Overload frame request (initiator).

Auto-resettable bit.
Set to send an overload frame after the next received message.
Cleared by the hardware at the beginning of transmission of the overload frame.

5

TTC

Network in Timer Trigger communication

0 - no TTC.
1 - node in TTC.

4

SYNCTTC

Synchronization of TTC

When this bit is set to "1" the TTC timer is caught on the last bit of the End Of Frame.
When this bit is set to "0" the TTC timer is caught on the Start Of Frame.
This bit is only used in the TTC mode.

3

AUTOBAUD

AUTOBAUD

0 - no autobaud
1 - autobaud mode.

2

TEST

Test mode. The test mode is intended for factory testing and not for customer use.

1

ENA/STB

Enable/Standby CAN controller

When this bit is set to “1’, it enables the CAN controller and its input clock.
When this bit is set to “0”, the on-going communication is terminated normally and the CAN controller
state of the machine is frozen (the ENCH bit of each message object does not change).
In the standby mode, the transmitter constantly provides a recessive level; the receiver is not activated
and the input clock is stopped in the CAN controller. During the disable mode, the registers and the
mailbox remain accessible.
Note that two clock periods are needed to start the CAN controller state of the machine.

0

GRES

General reset (software reset).

Auto-resettable bit. This reset command is ’ORed’ with the hardware reset in order to reset the
controller. After a reset, the controller is disabled.

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