Rainbow Electronics W79E8213R User Manual
Page 80
Preliminary W79E8213/W79E8213R Data Sheet
Publication Release Date: July 11, 2008
- 80 -
Revision A2
22. PULSE-WIDTH-MODULATED (PWM) OUTPUTS
The W79E8213 series have 4 Pulse Width Modulated (PWM) channels, and the PWM outputs are
PWM0(P0.1), PWM1(P1.6), PWM2(P1.7), PWM3(P0.0). The initial PWM outputs level
correspondingly depend on the PRHI level set prior to the chip reset. When PRHI set to high, PWM
output will initialize to high after chip reset; if PRHI set to low, PWM output will be initialize to low after
chip reset.
The W79E8213 series support 10-bits down counter with cpu clock as its input. The PWM counter
clock, has the frequency as F
CPWM
= F
OSC
/Prescaler. The two pre-scaler selectable bits FP[1:0] are
located at PWMCON3[3:2].
When the counter reaches underflow it will automatic reloaded from counter register. The PWM
frequency is given by: f
PWM
= F
CPWM
/ (PWMP+1), where PWMP is 10-bits register of PWMPH.1,
PWMPH.0 and PWMPL.7~PWMPL.0.
The counter register will be loaded with the PWMP register value when PWMRUN, load and PWMF
are equal to 1; the load bit will be automatically cleared to zero on the next clock cycle, and at the
same time the counter register value will be loaded to the 10 bits down counter. PWMF flag is set
when 10-bits down counter underflow, the PWMF flag can only be cleared by software.
The pulse width of each PWM output is determined by the Compare registers of PWM0L through
PWM3L and PWM0H through PWM3H. When PWM compare register is greater than 10-bits counter
register, the PWM output is low. Load bit has to be set to 1 for alteration of PWMn width. After the
new values are written to the PWMn registers, and if load bit is set to 1, the new PWMn values will be
loaded to the PWMn registers upon the next underflow. The PWM output high pulses width is given
by:
t
HI
= (PWMP – PWMn+1).
The following equations show the formula for period and duty:
Period
= (pwmp +1) * ioclock period * 1/prescaler
Duty
= duty * ioclock period
Note:
1.
If compare register is set to 000H, the PWMn output will stay at high, and if compare register is
set to 3FFH, the PWMn output will stuck at low until there is a change in the compare register.
[n = 0-3].
2.
During ICP mode, PWM pins will be tri-stated. PWM operation will be stop. When exit from ICP
mode, the PWM pins will follow the last SFR port values.