Rainbow Electronics ATmega128RFA1 User Manual

Atmega128rfa1, Atmega128rfa1 preliminary

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Table of contents

Document Outline

1 Pin Configurations
2 Disclaimer
3 Overview
- 3.1 Block Diagram
- 3.2 Pin Descriptions
- 3.3 Compatibility to ATmega1281/2561
4 Resources
5 About Code Examples
6 Data Retention
7 AVR CPU Core
- 7.1 Introduction
- 7.2 Architectural Overview
- 7.3 ALU - Arithmetic Logic Unit
- 7.4 Status Register
  - 7.4.1 SREG - Status Register
- 7.5 General Purpose Register File
  - 7.5.1 The X-register, Y-register, and Z-register
- 7.6 Stack Pointer
- 7.7 Instruction Execution Timing
- 7.8 Reset and Interrupt Handling
  - 7.8.1 Interrupt Response Time
8 AVR Memories
- 8.1 In-System Reprogrammable Flash Program Memory
- 8.2 SRAM Data Memory
  - 8.2.1 Data Memory Access Times
- 8.3 EEPROM Data Memory
  - 8.3.1 EEPROM Read Write Access
  - 8.3.2 Preventing EEPROM Corruption
- 8.4 EEPROM Register Description
- 8.5 I/O Memory
- 8.6 General Purpose I/O Registers
- 8.7 Other Port Registers
9 Low-Power 2.4 GHz Transceiver
- 9.1 Features
- 9.2 General Circuit Description
- 9.3 Transceiver to Microcontroller Interface
- 9.4 Operating Modes
  - 9.4.1 Basic Operating Mode
  - 9.4.2 Extended Operating Mode
- 9.5 Functional Description
- 9.6 Module Description
- 9.7 Radio Transceiver Usage
  - 9.7.1 Frame Receive Procedure
  - 9.7.2 Frame Transmit Procedure
- 9.8 Radio Transceiver Extended Feature Set
- 9.9 Continuous Transmission Test Mode
  - 9.9.1 Overview
  - 9.9.2 Configuration
- 9.10 Abbreviations
- 9.11 Reference Documents
- 9.12 Register Description
10 MAC Symbol Counter
- 10.1 Main Features
- 10.2 Clock source selection and Sleep/Active mode operation
- 10.3 32 bit Register Access (Atomic Read/Write)
- 10.4 Symbol Counter (32 bit, SCCNT)
- 10.5 Symbol Counter SFD Timestamp Register (32 bit, SCTSR, Read Only)
- 10.6 Symbol Counter Beacon Timestamp Register (32 bit, SCBTSR)
- 10.7 Compare Unit (3x 32 bit, SCOCR1, SCOCR2, SCOCR3)
- 10.8 Interrupt Control Registers
- 10.9 Backoff Slot Counter
- 10.10 Symbol Counter Usage
  - 10.10.1 SFD and Beacon Timestamp Generation
  - 10.10.2 Relative Compare Mode for Superframe Access Timing
- 10.11 Register Description
11 System Clock and Clock Options
- 11.1 Overview
- 11.2 Clock Systems and their Distribution
- 11.3 Clock Sources
  - 11.3.1 Default Clock Source
  - 11.3.2 Clock Start-up Sequence
- 11.4 Calibrated Internal RC Oscillator
- 11.5 128 kHz Internal Oscillator
- 11.6 External Clock
- 11.7 Transceiver Crystal Oscillator
- 11.8 Clock Output Buffer
- 11.9 Timer/Counter Oscillator
- 11.10 System Clock Prescaler
- 11.11 Register Description
  - 11.11.1 OSCCAL - Oscillator Calibration Value
  - 11.11.2 CLKPR - Clock Prescale Register
12 Power Management and Sleep Modes
- 12.1 Deep-Sleep Mode
- 12.2 AVR Microcontroller Sleep Modes
- 12.3 Power Reduction Register
- 12.4 Minimizing Power Consumption
- 12.5 Supply Voltage and Leakage Control
- 12.6 Register Description
13 System Control and Reset
- 13.1 Resetting the AVR
- 13.2 Reset Sources
- 13.3 Internal Voltage Reference
- 13.4 Watchdog Timer
  - 13.4.1 Features
  - 13.4.2 Overview
- 13.5 Register Description
  - 13.5.1 MCUSR - MCU Status Register
  - 13.5.2 WDTCSR - Watchdog Timer Control Register
14 I/O-Ports
- 14.1 Introduction
- 14.2 Ports as General Digital I/O
- 14.3 Alternate Port Functions
- 14.4 Register Description
15 Interrupts
- 15.1 Interrupt Vectors in ATmega128RFA1
- 15.2 Reset and Interrupt Vector Placement
- 15.3 Moving Interrupts Between Application and Boot Section
- 15.4 Register Description
  - 15.4.1 MCUCR - MCU Control Register
16 External Interrupts
- 16.1 Pin Change Interrupt Timing
- 16.2 Register Description
17 8-bit Timer/Counter0 with PWM
- 17.1 Features
- 17.2 Overview
  - 17.2.1 Registers
  - 17.2.2 Definitions
- 17.3 Timer/Counter Clock Sources
- 17.4 Counter Unit
- 17.5 Output Compare Unit
- 17.6 Compare Match Output Unit
  - 17.6.1 Compare Output Mode and Waveform Generation
- 17.7 Modes of Operation
- 17.8 Timer/Counter Timing Diagrams
- 17.9 Register Description
18 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)
- 18.1 Features
- 18.2 Overview
  - 18.2.1 Registers
  - 18.2.2 Definitions
- 18.3 Accessing 16-bit Registers
  - 18.3.1 Reusing the Temporary High Byte Register
- 18.4 Timer/Counter Clock Sources
- 18.5 Counter Unit
- 18.6 Input Capture Unit
- 18.7 Output Compare Units
- 18.8 Compare Match Output Unit
  - 18.8.1 Compare Output Mode and Waveform Generation
- 18.9 Modes of Operation
- 18.10 Timer/Counter Timing Diagrams
- 18.11 Register Description
19 Timer/Counter 0, 1, 3, 4, and 5 Prescaler
- 19.1 Internal Clock Source
- 19.2 Prescaler Reset
- 19.3 External Clock Source
- 19.4 Register Description
  - 19.4.1 GTCCR - General Timer/Counter Control Register
20 Output Compare Modulator (OCM1C0A)
- 20.1 Overview
- 20.2 Description
- 20.3 Timing Example
21 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 21.1 Features
- 21.2 Overview
  - 21.2.1 Registers
  - 21.2.2 Definitions
- 21.3 Timer/Counter Clock Sources
- 21.4 Counter Unit
- 21.5 Modes of Operation
- 21.6 Output Compare Unit
- 21.7 Compare Match Output Unit
  - 21.7.1 Compare Output Mode and Waveform Generation
- 21.8 Timer/Counter Timing Diagrams
- 21.9 Asynchronous Operation of Timer/Counter2
- 21.10 Timer/Counter Prescaler
- 21.11 Register Description
22 SPI- Serial Peripheral Interface
- 22.1 Features
- 22.2 Functional Description
- 22.3 Pin Functionality
- 22.4 Register Description
23 USART
- 23.1 Features
- 23.2 Overview
- 23.3 Clock Generation
- 23.4 Frame Formats
  - 23.4.1 Parity Bit Calculation
- 23.5 USART Initialization
- 23.6 Data Transmission - The USART Transmitter
- 23.7 Data Reception - The USART Receiver
- 23.8 Asynchronous Data Reception
- 23.9 Multi-processor Communication Mode
  - 23.9.1 Using MPCMn
- 23.10 Register Description
- 23.11 Examples of Baud Rate Setting
24 USART in SPI Mode
- 24.1 Overview
- 24.2 USART MSPIM vs. SPI
  - 24.2.1 Clock Generation
- 24.3 SPI Data Modes and Timing
- 24.4 Frame Formats
  - 24.4.1 USART MSPIM Initialization
- 24.5 Data Transfer
  - 24.5.1 Transmitter and Receiver Flags and Interrupts
  - 24.5.2 Disabling the Transmitter or Receiver
- 24.6 USART MSPIM Register Description
25 2-wire Serial Interface
- 25.1 Features
- 25.2 2-wire Serial Interface Bus Definition
  - 25.2.1 TWI Terminology
  - 25.2.2 Electrical Interconnection
- 25.3 Data Transfer and Frame Format
- 25.4 Multi-master Bus Systems, Arbitration and Synchronization
- 25.5 Overview of the TWI Module
- 25.6 Using the TWI
- 25.7 Transmission Modes
- 25.8 Multi-master Systems and Arbitration
- 25.9 Register Description
26 AC - Analog Comparator
- 26.1 Analog Comparator Multiplexed Input
- 26.2 Register Description
27 ADC - Analog to Digital Converter
- 27.1 Features
- 27.2 Operation
- 27.3 ADC Start-Up
- 27.4 Starting a Conversion
- 27.5 Pre-scaling and Conversion Timing
- 27.6 Changing Channel or Reference Selection
- 27.7 ADC Noise Canceller
- 27.8 ADC Conversion Result
- 27.9 Internal Temperature Measurement
- 27.10 SRAM DRT Voltage Measurement
- 27.11 Register Description
28 JTAG Interface and On-chip Debug System
- 28.1 Features
- 28.2 Overview
- 28.3 TAP - Test Access Port
- 28.4 TAP Controller
- 28.5 Using the Boundary-scan Chain
- 28.6 Using the On-chip Debug System
- 28.7 On-chip Debug Specific JTAG Instructions
- 28.8 Using the JTAG Programming Capabilities
- 28.9 Bibliography
- 28.10 On-chip Debug Related Register in I/O Memory
  - 28.10.1 OCDR - On-Chip Debug Register
29 IEEE 1149.1 (JTAG) Boundary-scan
- 29.1 Features
- 29.2 System Overview
- 29.3 Data Registers
- 29.4 Boundary-scan Specific JTAG Instructions
- 29.5 Boundary-scan Chain
- 29.6 Boundary-scan Related Register in I/O Memory
  - 29.6.1 MCUCR - MCU Control Register
  - 29.6.2 MCUSR - MCU Status Register
- 29.7 Boundary-scan Description Language Files
- 29.8 ATmega128RFA1 Boundary-scan Order
30 Boot Loader Support - Read-While-Write Self-Programming
- 30.2 Application and Boot Loader Flash Sections
  - 30.2.1 Application Section
  - 30.2.2 BLS - Boot Loader Section
- 30.3 Read-While-Write and No Read-While-Write Flash Sections
  - 30.3.1 RWW - Read-While-Write Section
  - 30.3.2 NRWW - No Read-While-Write Section
- 30.4 Boot Loader Lock Bits
  - 30.4.1 Entering the Boot Loader Program
- 30.5 Addressing the Flash During Self-Programming
- 30.6 Self-Programming the Flash
- 30.7 Register Description
  - 30.7.1 SPMCSR - Store Program Memory Control Register
  - 30.7.2 NEMCR - Flash Extended-Mode Control-Register
31 Memory Programming
- 31.1 Program And Data Memory Lock Bits
- 31.2 Fuse Bits
  - 31.2.1 Latching of Fuses
- 31.3 Signature Bytes
- 31.4 Calibration Byte
- 31.5 Page Size
- 31.6 Parallel Programming Parameters, Pin Mapping, and Commands
  - 31.6.1 Signal Names
- 31.7 Parallel Programming
- 31.8 Serial Downloading
- 31.9 Programming via the JTAG Interface
32 Application Circuits
- 32.1 Basic Application Schematic
- 32.2 Extended Feature Set Application Schematic
33 Register Summary
34 Electrical Characteristics
- 34.1 Absolute Maximum Ratings
  - 34.1.1 Recommended Operating Range
  - 34.1.2 Digital Pin Characteristics
- 34.2 Clock Characteristics
  - 34.2.1 Calibrated Internal RC Oscillator Accuracy
  - 34.2.2 External Clock Drive
- 34.3 System and Reset Characteristics
- 34.4 Power Management Electrical Characteristics
  - 34.4.1 Power Switches
  - 34.4.2 Voltage Regulators
- 34.5 2-wire Serial Interface Characteristics
- 34.6 SPI Timing Characteristics
- 34.7 ADC Characteristics
- 34.8 Transceiver Electrical Characteristics
35 Typical Characteristics
- 35.1 Internal Oscillator Speed
36 Ordering Information
37 Packaging Information
38 Errata
- 38.1 ATmega128RFA1 revision D (1.2)
- 38.2 ATmega128RFA1 revision C (1.1)
- 38.3 ATmega128RFA1 revision AB (1.0)
- 38.4 Compiler package WinAVR-20090313
- 38.5 Detailed errata description
39 Revision history
Table of Contents