Rainbow Electronics DS1286 - Manual (Page 6)

DS1286
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TIME OF DAY REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day data in BCD. Ten bits within these eight registers
are not used and will always read 0 regardless of how they are written. Bits 6 and 7 in the Months
Register (9) are binary bits. When set to logic 0, EOSC (bit 7) enables the Real Time Clock oscillator.
This bit is set to logic 1 as shipped from Dallas Semiconductor to prevent lithium energy consumption
during storage and shipment. This bit will normally be turned on by the user during device initialization.
However, the oscillator can be turned on and off as necessary by setting this bit to the appropriate level.
Bit 6 of this same byte controls the Square Wave Output (Pin 23). When set to logic 0, the Square Wave
Output pin will output a 1024 Hz Square Wave Signal. When set to logic 1 the Square Wave Output pin
is in a high impedance state. Bit 6 of the Hours Register is defined as the 12- or 24- hour Select Bit. When
set to logic 1, the 12-hour format is selected. In the 12-hour format, bit 5 is the AM/PM bit with logic 1
being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). The Time of Day registers
are updated every .01 seconds from the real time clock, except when the TE bit (bit 7 of Register B) is set
low or the clock oscillator is not running. The preferred method of synchronizing data access to and from
the Watchdog Timekeeper is to access the Command Register by doing a write cycle to address location
0B and setting the TE bit (Transfer Enable ) to a logic 0. This will freeze the External Time of Day
registers at the present recorded time, allowing access to occur without danger of simultaneous update.
When the watch registers have been read or written, a second write cycle to location 0B, setting the TE
bit to a logic 1, will put the Time of Day registers back to being updated every 0.01 second. No time is
lost in the real time clock because the internal copy of the Time of Day register buffers is continually
incremented while the external memory registers are frozen.
An alternate method of reading and writing the Time of Day registers is to ignore synchronization.
However, any single read may give erroneous data as the real time clock may be in the process of
updating the external memory registers as data is being read. The internal copies of seconds through years
are incremented and Time of Day Alarm is checked during the period that hundreds of seconds read 99
and are transferred to the external register when hundredths of seconds roll from 99 to 00. A way of
making sure data is valid is to do multiple reads and compare. Writing the registers can also produce
erroneous results for the same reasons. A way of making sure that the write cycle has caused proper
update is to do read verifies and re-execute the write cycle if data is not correct. While the possibility of
erroneous results from reads and write cycles has been stated, it is worth noting that the probability of an
incorrect result is kept to a minimum due to the redundant structure of the Watchdog Timekeeper.
TIME OF DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the Time of Day Alarm registers. Bits 3, 4, 5, and 6 of Register 7 will
always read 0 regardless of how they are written. Bit 7 of Registers 3, 5, and 7 are mask bits (Figure 3).
When all of the mask bits are logic 0, a Time of Day Alarm will only occur when Registers 2, 4, and 6
match the values stored in Registers 3, 5, and 7. An alarm will be generated every day when bit 7 of
Register 7 is set to a logic 1. Similarly, an alarm is generated every hour when bit 7 of Registers 7 and 5
is set to a logic 1. When bit 7 of Registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute
when Register 1 (seconds) rolls from 59 to 00.
Time of Day Alarm registers are written and read in the same format as the Time of Day registers. The
Time of Day Alarm Flag and Interrupt is always cleared when Alarm registers are read or written.