Rainbow Electronics DS1286 - Manual (Page 7)

DS1286
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WATCHDOG ALARM REGISTERS
Registers C and D contain the time for the Watchdog Alarm. The two registers contain a time count from
to 99.99 seconds in BCD. The value written into the Watchdog Alarm Registers can be written or read in
any order. Any access to Registers C or D will cause the Watchdog Alarm to reinitialize and clears the
Watchdog Flag bit and the Watchdog Interrupt Output. When a new value is entered or the Watchdog
Registers are read, the Watchdog Timer will start counting down from the entered value to 0. When 0 is
reached, the Watchdog Interrupt Output will go to the active state. The Watchdog Timer countdown is
interrupted and reinitialized back to the entered value every time either of the registers is accessed. In this
manner, controlled periodic accesses to the Watchdog Timer can prevent the Watchdog Alarm from ever
going to an active level. If access does not occur, countdown alarm will be repetitive. The Watchdog
Alarm registers always read the entered value. The actual countdown register is internal and is not
readable. Writing Registers C and D to 0 will disable the Watchdog Alarm feature.
COMMAND REGISTER
Address location 0B is the Command Register where mask bits, control bits, and flag bits reside. Bit 0 is
the Time of Day Alarm Flag (TDF). When this bit is set internally to a logic 1, an alarm has occurred.
The time of the alarm can be determined by reading the Time of Day Alarm registers. However, if the
transfer enable bit is set to logic 0 the Time of Day registers may not reflect the exact time that the alarm
occurred. This bit is read only and writing this register has no effect on the bit. The bit is reset when any
of the Time of Day Alarm registers are read. Bit 1 is the Watchdog Alarm Flag (WAF). When this bit is
set internally to a logic 1, a Watchdog Alarm has occurred. This bit is read only and writing this register
has no effect on the bit. The bit is reset when any of the Watchdog Alarm registers are accessed. Bit 2 of
the Command Register contains the Time of Day Alarm Mask Bit (TDM). When this bit is written to a
logic 1, the Time of Day Alarm Interrupt Output is deactivated regardless of the value of the Time of Day
Alarm Flag. When TDM is set to logic 0, the Time of Day Interrupt Output will go to the active state,
which is determined by bits 0, 4, 5, and 6 of the Command Register. Bit 3 of the Command Register
contains the Watchdog Alarm Mask bit (WAM). When this bit is written to a logic 1, the Watchdog
Interrupt Output is deactivated regardless of the value in the Watchdog Alarm registers. When WAM is
set to logic 0, the Watchdog Interrupt Output will go to the active state which is determined by bits 1, 4,
5, and 6 of the Command Register. These 4 bits define how Interrupt Output Pins INTA and INTB (INTB)
will be operated. Bit 4 of the Command Register determines whether both interrupts will output a pulse or
level when activated. If bit 4 is set to logic 1, the pulse mode is selected and INTA will sink current for a
minimum of 3 ms and then release. Output INTB (INTB) will either sink or source current for a minimum
of 3 ms depending on the level of bit 5. When bit 5 is set to logic 1, the B interrupt will source current.
When bit 5 is set to logic 0, the B interrupt will sink current. Bit 6 of the Command Register directs
which type of interrupt will be present on interrupt pins INTA or INTB (INTB). When set to logic 1, INTA
becomes the Time of Day Alarm Interrupt pin and INTB (INTB) becomes the Watchdog Interrupt pin.
When bit 6 is set to logic 0, the interrupt functions are reversed such that the Time of Day Alarm will be
output on INTB (INTB) and the Watchdog Interrupt will be output on INTA . Caution should be exercised
when dynamically setting this bit as the interrupts will be reversed even if in an active state. Bit 7 of the
Command Register is for Transfer Enable (TE). The function of this bit is described in the Time of Day
registers.