Rainbow Electronics HT24LC04 - Manual (Page 4)

HT24LC04
Rev. 1.20 4 November 5, 2002
· Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
· Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth
clock cycle.
Device addressing
The 4K EEPROM devices require an 8-bit device ad-
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to diagram showing the
Device Address). This is common to all the EEPROM
device.
The next three bits are the A2, A1 and A0 device ad-
dress bits for the 1K/2K EEPROM. These three bits
must compare to their corresponding hard-wired input
pins.
The 4K EEPROM only use the A2 and A1 device ad-
dress bits with the third bit as a memory page address
bit. The two device address bits must compare to their
corresponding hardwired input pins. The A0 pin is not
connected.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
Write operations
· Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
· Page write
The 4K device is capable of 16-byte page writes.
A page write is initiated the same as byte write, but the
microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the
EEPROM acknowledges the receipt of the first data
word, the microcontroller can transmit up to fifteen
more data words. The EEPROM will respond with a
z e r o a f t e r e a c h d a t a w o r d r e c e i v e d . T h e
microcontroller must terminate the page write se-
quence with a stop condition.
The data word address lower four bits are internally in-
cremented following the receipt of each data word.
The higher data word address bits are not incre-
mented, retaining the memory page row location (re-
fer to Page write timing).
S C L
S D A
D a t a a l l o w e d
t o c h a n g e
A d d r e s s o r
a c k n o w l e d g e
v a l i d
S t o p
c o n d i t i o n
S t a r t
c o n d i t i o n
R / W 1 0 A 2 A 1 A 0
D e v i c e A d d r e s s
1 0
R / W
A 2 A 1 A 0 S P
D e v i c e a d d r e s s W o r d a d d r e s s D A T A
A C K
S t o p
S t a r t
S D A
A C K A C K
Byte write timing
P
D e v i c e a d d r e s s W o r d a d d r e s s D A T A n
A C K
S t o p
S t a r t
S D A
A C K A C K
S
A C K
D A T A n + 1 D A T A n + x
Page write timing