Ds92001 pin description (soic and llp), Ac test circuits and timing diagrams – Rainbow Electronics DS92001 User Manual
Page 7
Advertising
AC Test Circuits and Timing Diagrams
(Continued)
DS92001 Pin Description (SOIC and LLP)
Pin Name
Pin #
Input/Output
Description
GND
1
P
Ground
IN −
2
I
Inverting receiver B/LVDS input pin
IN+
3
I
Non-inverting receiver B/LVDS input pin
LOS
4
O
Loss of Signal output pin. LOS is asserted low while signal is invalid.
See Applications Information section.
V
CC
5
P
Power Supply, 3.3V
±
0.3V.
OUT+
6
O
Non-inverting driver BLVDS output pin
OUT -
7
O
Inverting driver BLVDS output pin
EN
8
I
Enable pin. When EN is LOW, the driver is disabled and the BLVDS
outputs are in TRI-STATE. When EN is HIGH, the driver is enabled.
LVCMOS/LVTTL levels.
GND
DAP
P
LLP Package Ground
20024742
FIGURE 9. LOS Output Waveforms for Propagation Delay, and Rise/Fall Times
DS92001
www.national.com
7
Advertising