Rainbow Electronics AT90S2313 - Manual (Page 45)

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AT90S2313
0839I–AVR–06/02
UART Control
The UART I/O Data Register –
UDR
The UDR Register is actually two physically separate registers sharing the same I/O
address. When writing to the register, the UART Transmit Data Register is written.
When reading from UDR, the UART Receive Data Register is read.
UART Status Register – USR
The USR Register is a read-only register providing information on the UART status.
• Bit 7 – RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift
Register to UDR. The bit is set regardless of any detected framing errors. When the
RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when
RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception
is used, the UART Receive Complete Interrupt routine must read UDR in order to clear
RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
• Bit 6 – TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit
Shift Register has been shifted out and no new data has been written to UDR. This flag
is especially useful in half-duplex communications interfaces, where a transmitting appli-
cation must enter Receive mode and free the communications bus immediately after
completing the transmission.
When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete
interrupt to be executed. TXC is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical
“1” to the bit.
• Bit 5 – UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is transferred to the Transmit Shift
Register. Setting of this bit indicates that the transmitter is ready to receive a new char-
acter for transmission.
When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt is executed
as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data
transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in
order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine
terminates.
UDRE is set (one) during reset to indicate that the transmitter is ready.
Bit 7 6 5 4 3 2 1 0
$0C ($2C) MSB LSB UDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
$0B ($2B) RXC TXC UDRE FE OR – – – USR
Read/Write R R/W R R R R R R
Initial value 0 0 1 0 0 0 0 0