Rainbow Electronics DS1874 - Manual (Page 15)

BIAS and MODULATION Registers as a
Function of Transmit Disable (TXD)
If TXD is asserted (logic 1) during normal operation, the
outputs are disabled within t
OFF . When TXD is deassert-
ed (logic 0), the DS1874 sets the MODULATION regis-
ter with the value associated with the present
temperature, and initializes the BIAS register using the
same search algorithm as done at startup. When
asserted, soft TXD (TXDC) (Lower Memory, Register
6Eh) would allow a software control identical to the TXD
pin (see Figure 3).
APC and Quick-Trip Timing
As shown in Figure 4, the DS1874’s input comparator is
shared between the APC control loop and the quick-
trip alarms (TXP HI, TXP LO, LOS, and BIAS HI). The
comparator polls the alarms in a multiplexed sequence.
Five of every eight comparator readings are used for
APC loop bias-current control. The other three updates
are used to check the HTXP/LTXP (monitor diode volt-
age), the HBATH (MON1), and LOS (MON3) signals
against the internal APC, BIAS, and MON3 reference,
respectively. If the last APC comparison was higher
than the APC set point, it makes an HTXP comparison,
and if it is lower, it makes an LTXP comparison.
Depending on the results of the comparison, the corre-
sponding alarms and warnings (TXP HI, TXP LO) are
asserted or deasserted.
The DS1874 has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options and time
delays resulting from writing values to the MAX3798/
MAX3799’s bias DAC. The UPDATE RATE register
(Table 02h, Register 88h) determines the sampling
time. Samples occur at a regular interval, t
REP
. Table 2
shows the sample rate options available. Any quick-trip
alarm that is detected by default remains active until a
subsequent comparator sample shows the condition no
longer exists. A second bias current monitor (BIAS
MAX) compares the MAX3798/MAX3799’s BIAS DAC’s
code to a digital value stored in the IBIASMAX register.
This comparison is made at every bias current update
to ensure that a high-bias current is quickly detected.
An APC sample that requires an update of the BIAS
register causes subsequent APC samples to be
DS1874
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 15
APC QUICK-TRIP SAMPLE TIMES
HBIAS
SAMPLE
HBIAS
SAMPLE
LOS
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
HTXP/LTXP
SAMPLE
t
REP
Figure 4. APC Loop and Quick-Trip Sample Timing
Table 2. Update Rate Timing
APC_SR[2:0]
SAMPLE PERIOD (tREP)
(ns)
000b 800
001b 1200
010b 1600
011b 2000
100b 2800
101b 3200
110b 4400
111b 6400
t OFF
t OFF
t ON
t ON
TXD
BIAS REGISTER
MODULATION REGISTER
Figure 3. TXD Timing